1 // Copyright 2016 The Go Authors. All rights reserved.
2 // Use of this source code is governed by a BSD-style
3 // license that can be found in the LICENSE file.
4
5 (Add(Ptr|32|16|8) ...) => (ADD ...)
6 (Add(32|64)F ...) => (ADD(F|D) ...)
7
8 (Select0 (Add32carry <t> x y)) => (ADD <t.FieldType(0)> x y)
9 (Select1 (Add32carry <t> x y)) => (SGTU <typ.Bool> x (ADD <t.FieldType(0)> x y))
10 (Add32withcarry <t> x y c) => (ADD c (ADD <t> x y))
11
12 (Sub(Ptr|32|16|8) ...) => (SUB ...)
13 (Sub(32|64)F ...) => (SUB(F|D) ...)
14
15 (Select0 (Sub32carry <t> x y)) => (SUB <t.FieldType(0)> x y)
16 (Select1 (Sub32carry <t> x y)) => (SGTU <typ.Bool> (SUB <t.FieldType(0)> x y) x)
17 (Sub32withcarry <t> x y c) => (SUB (SUB <t> x y) c)
18
19 (Mul(32|16|8) ...) => (MUL ...)
20 (Mul(32|64)F ...) => (MUL(F|D) ...)
21
22 (Hmul(32|32u) x y) => (Select0 (MUL(T|TU) x y))
23 (Mul32uhilo ...) => (MULTU ...)
24
25 (Div32 x y) => (Select1 (DIV x y))
26 (Div32u x y) => (Select1 (DIVU x y))
27 (Div16 x y) => (Select1 (DIV (SignExt16to32 x) (SignExt16to32 y)))
28 (Div16u x y) => (Select1 (DIVU (ZeroExt16to32 x) (ZeroExt16to32 y)))
29 (Div8 x y) => (Select1 (DIV (SignExt8to32 x) (SignExt8to32 y)))
30 (Div8u x y) => (Select1 (DIVU (ZeroExt8to32 x) (ZeroExt8to32 y)))
31 (Div(32|64)F ...) => (DIV(F|D) ...)
32
33 (Mod32 x y) => (Select0 (DIV x y))
34 (Mod32u x y) => (Select0 (DIVU x y))
35 (Mod16 x y) => (Select0 (DIV (SignExt16to32 x) (SignExt16to32 y)))
36 (Mod16u x y) => (Select0 (DIVU (ZeroExt16to32 x) (ZeroExt16to32 y)))
37 (Mod8 x y) => (Select0 (DIV (SignExt8to32 x) (SignExt8to32 y)))
38 (Mod8u x y) => (Select0 (DIVU (ZeroExt8to32 x) (ZeroExt8to32 y)))
39
40 // math package intrinsics
41 (Abs ...) => (ABSD ...)
42
43 // (x + y) / 2 with x>=y becomes (x - y) / 2 + y
44 (Avg32u <t> x y) => (ADD (SRLconst <t> (SUB <t> x y) [1]) y)
45
46 (And(32|16|8) ...) => (AND ...)
47 (Or(32|16|8) ...) => (OR ...)
48 (Xor(32|16|8) ...) => (XOR ...)
49
50 // constant shifts
51 // generic opt rewrites all constant shifts to shift by Const64
52 (Lsh32x64 x (Const64 [c])) && uint32(c) < 32 => (SLLconst x [int32(c)])
53 (Rsh32x64 x (Const64 [c])) && uint32(c) < 32 => (SRAconst x [int32(c)])
54 (Rsh32Ux64 x (Const64 [c])) && uint32(c) < 32 => (SRLconst x [int32(c)])
55 (Lsh16x64 x (Const64 [c])) && uint32(c) < 16 => (SLLconst x [int32(c)])
56 (Rsh16x64 x (Const64 [c])) && uint32(c) < 16 => (SRAconst (SLLconst <typ.UInt32> x [16]) [int32(c+16)])
57 (Rsh16Ux64 x (Const64 [c])) && uint32(c) < 16 => (SRLconst (SLLconst <typ.UInt32> x [16]) [int32(c+16)])
58 (Lsh8x64 x (Const64 [c])) && uint32(c) < 8 => (SLLconst x [int32(c)])
59 (Rsh8x64 x (Const64 [c])) && uint32(c) < 8 => (SRAconst (SLLconst <typ.UInt32> x [24]) [int32(c+24)])
60 (Rsh8Ux64 x (Const64 [c])) && uint32(c) < 8 => (SRLconst (SLLconst <typ.UInt32> x [24]) [int32(c+24)])
61
62 // large constant shifts
63 (Lsh32x64 _ (Const64 [c])) && uint32(c) >= 32 => (MOVWconst [0])
64 (Rsh32Ux64 _ (Const64 [c])) && uint32(c) >= 32 => (MOVWconst [0])
65 (Lsh16x64 _ (Const64 [c])) && uint32(c) >= 16 => (MOVWconst [0])
66 (Rsh16Ux64 _ (Const64 [c])) && uint32(c) >= 16 => (MOVWconst [0])
67 (Lsh8x64 _ (Const64 [c])) && uint32(c) >= 8 => (MOVWconst [0])
68 (Rsh8Ux64 _ (Const64 [c])) && uint32(c) >= 8 => (MOVWconst [0])
69
70 // large constant signed right shift, we leave the sign bit
71 (Rsh32x64 x (Const64 [c])) && uint32(c) >= 32 => (SRAconst x [31])
72 (Rsh16x64 x (Const64 [c])) && uint32(c) >= 16 => (SRAconst (SLLconst <typ.UInt32> x [16]) [31])
73 (Rsh8x64 x (Const64 [c])) && uint32(c) >= 8 => (SRAconst (SLLconst <typ.UInt32> x [24]) [31])
74
75 // shifts
76 // hardware instruction uses only the low 5 bits of the shift
77 // we compare to 32 to ensure Go semantics for large shifts
78 (Lsh32x32 <t> x y) => (CMOVZ (SLL <t> x y) (MOVWconst [0]) (SGTUconst [32] y))
79 (Lsh32x16 <t> x y) => (CMOVZ (SLL <t> x (ZeroExt16to32 y) ) (MOVWconst [0]) (SGTUconst [32] (ZeroExt16to32 y)))
80 (Lsh32x8 <t> x y) => (CMOVZ (SLL <t> x (ZeroExt8to32 y) ) (MOVWconst [0]) (SGTUconst [32] (ZeroExt8to32 y)))
81
82 (Lsh16x32 <t> x y) => (CMOVZ (SLL <t> x y) (MOVWconst [0]) (SGTUconst [32] y))
83 (Lsh16x16 <t> x y) => (CMOVZ (SLL <t> x (ZeroExt16to32 y) ) (MOVWconst [0]) (SGTUconst [32] (ZeroExt16to32 y)))
84 (Lsh16x8 <t> x y) => (CMOVZ (SLL <t> x (ZeroExt8to32 y) ) (MOVWconst [0]) (SGTUconst [32] (ZeroExt8to32 y)))
85
86 (Lsh8x32 <t> x y) => (CMOVZ (SLL <t> x y) (MOVWconst [0]) (SGTUconst [32] y))
87 (Lsh8x16 <t> x y) => (CMOVZ (SLL <t> x (ZeroExt16to32 y) ) (MOVWconst [0]) (SGTUconst [32] (ZeroExt16to32 y)))
88 (Lsh8x8 <t> x y) => (CMOVZ (SLL <t> x (ZeroExt8to32 y) ) (MOVWconst [0]) (SGTUconst [32] (ZeroExt8to32 y)))
89
90 (Rsh32Ux32 <t> x y) => (CMOVZ (SRL <t> x y) (MOVWconst [0]) (SGTUconst [32] y))
91 (Rsh32Ux16 <t> x y) => (CMOVZ (SRL <t> x (ZeroExt16to32 y) ) (MOVWconst [0]) (SGTUconst [32] (ZeroExt16to32 y)))
92 (Rsh32Ux8 <t> x y) => (CMOVZ (SRL <t> x (ZeroExt8to32 y) ) (MOVWconst [0]) (SGTUconst [32] (ZeroExt8to32 y)))
93
94 (Rsh16Ux32 <t> x y) => (CMOVZ (SRL <t> (ZeroExt16to32 x) y) (MOVWconst [0]) (SGTUconst [32] y))
95 (Rsh16Ux16 <t> x y) => (CMOVZ (SRL <t> (ZeroExt16to32 x) (ZeroExt16to32 y) ) (MOVWconst [0]) (SGTUconst [32] (ZeroExt16to32 y)))
96 (Rsh16Ux8 <t> x y) => (CMOVZ (SRL <t> (ZeroExt16to32 x) (ZeroExt8to32 y) ) (MOVWconst [0]) (SGTUconst [32] (ZeroExt8to32 y)))
97
98 (Rsh8Ux32 <t> x y) => (CMOVZ (SRL <t> (ZeroExt8to32 x) y) (MOVWconst [0]) (SGTUconst [32] y))
99 (Rsh8Ux16 <t> x y) => (CMOVZ (SRL <t> (ZeroExt8to32 x) (ZeroExt16to32 y) ) (MOVWconst [0]) (SGTUconst [32] (ZeroExt16to32 y)))
100 (Rsh8Ux8 <t> x y) => (CMOVZ (SRL <t> (ZeroExt8to32 x) (ZeroExt8to32 y) ) (MOVWconst [0]) (SGTUconst [32] (ZeroExt8to32 y)))
101
102 (Rsh32x32 x y) => (SRA x ( CMOVZ <typ.UInt32> y (MOVWconst [31]) (SGTUconst [32] y)))
103 (Rsh32x16 x y) => (SRA x ( CMOVZ <typ.UInt32> (ZeroExt16to32 y) (MOVWconst [31]) (SGTUconst [32] (ZeroExt16to32 y))))
104 (Rsh32x8 x y) => (SRA x ( CMOVZ <typ.UInt32> (ZeroExt8to32 y) (MOVWconst [31]) (SGTUconst [32] (ZeroExt8to32 y))))
105
106 (Rsh16x32 x y) => (SRA (SignExt16to32 x) ( CMOVZ <typ.UInt32> y (MOVWconst [31]) (SGTUconst [32] y)))
107 (Rsh16x16 x y) => (SRA (SignExt16to32 x) ( CMOVZ <typ.UInt32> (ZeroExt16to32 y) (MOVWconst [31]) (SGTUconst [32] (ZeroExt16to32 y))))
108 (Rsh16x8 x y) => (SRA (SignExt16to32 x) ( CMOVZ <typ.UInt32> (ZeroExt8to32 y) (MOVWconst [31]) (SGTUconst [32] (ZeroExt8to32 y))))
109
110 (Rsh8x32 x y) => (SRA (SignExt16to32 x) ( CMOVZ <typ.UInt32> y (MOVWconst [31]) (SGTUconst [32] y)))
111 (Rsh8x16 x y) => (SRA (SignExt16to32 x) ( CMOVZ <typ.UInt32> (ZeroExt16to32 y) (MOVWconst [31]) (SGTUconst [32] (ZeroExt16to32 y))))
112 (Rsh8x8 x y) => (SRA (SignExt16to32 x) ( CMOVZ <typ.UInt32> (ZeroExt8to32 y) (MOVWconst [31]) (SGTUconst [32] (ZeroExt8to32 y))))
113
114 // rotates
115 (RotateLeft8 <t> x (MOVWconst [c])) => (Or8 (Lsh8x32 <t> x (MOVWconst [c&7])) (Rsh8Ux32 <t> x (MOVWconst [-c&7])))
116 (RotateLeft16 <t> x (MOVWconst [c])) => (Or16 (Lsh16x32 <t> x (MOVWconst [c&15])) (Rsh16Ux32 <t> x (MOVWconst [-c&15])))
117 (RotateLeft32 <t> x (MOVWconst [c])) => (Or32 (Lsh32x32 <t> x (MOVWconst [c&31])) (Rsh32Ux32 <t> x (MOVWconst [-c&31])))
118 (RotateLeft64 <t> x (MOVWconst [c])) => (Or64 (Lsh64x32 <t> x (MOVWconst [c&63])) (Rsh64Ux32 <t> x (MOVWconst [-c&63])))
119
120 // unary ops
121 (Neg(32|16|8) ...) => (NEG ...)
122 (Neg(32|64)F ...) => (NEG(F|D) ...)
123
124 (Com(32|16|8) x) => (NORconst [0] x)
125
126 (Sqrt ...) => (SQRTD ...)
127 (Sqrt32 ...) => (SQRTF ...)
128
129 (Ctz(32|16|8)NonZero ...) => (Ctz32 ...)
130
131 // count trailing zero
132 // 32 - CLZ(x&-x - 1)
133 (Ctz32 <t> x) => (SUB (MOVWconst [32]) (CLZ <t> (SUBconst <t> [1] (AND <t> x (NEG <t> x)))))
134 (Ctz16 x) => (Ctz32 (Or32 <typ.UInt32> x (MOVWconst [1<<16])))
135 (Ctz8 x) => (Ctz32 (Or32 <typ.UInt32> x (MOVWconst [1<<8])))
136
137 // bit length
138 (BitLen32 <t> x) => (SUB (MOVWconst [32]) (CLZ <t> x))
139 (BitLen(16|8) x) => (BitLen32 (ZeroExt(16|8)to32 x))
140
141 // boolean ops -- booleans are represented with 0=false, 1=true
142 (AndB ...) => (AND ...)
143 (OrB ...) => (OR ...)
144 (EqB x y) => (XORconst [1] (XOR <typ.Bool> x y))
145 (NeqB ...) => (XOR ...)
146 (Not x) => (XORconst [1] x)
147
148 // constants
149 (Const(32|16|8) [val]) => (MOVWconst [int32(val)])
150 (Const(32|64)F ...) => (MOV(F|D)const ...)
151 (ConstNil) => (MOVWconst [0])
152 (ConstBool [t]) => (MOVWconst [b2i32(t)])
153
154 // truncations
155 // Because we ignore high parts of registers, truncates are just copies.
156 (Trunc16to8 ...) => (Copy ...)
157 (Trunc32to8 ...) => (Copy ...)
158 (Trunc32to16 ...) => (Copy ...)
159
160 // Zero-/Sign-extensions
161 (ZeroExt8to16 ...) => (MOVBUreg ...)
162 (ZeroExt8to32 ...) => (MOVBUreg ...)
163 (ZeroExt16to32 ...) => (MOVHUreg ...)
164
165 (SignExt8to16 ...) => (MOVBreg ...)
166 (SignExt8to32 ...) => (MOVBreg ...)
167 (SignExt16to32 ...) => (MOVHreg ...)
168
169 (Signmask x) => (SRAconst x [31])
170 (Zeromask x) => (NEG (SGTU x (MOVWconst [0])))
171 (Slicemask <t> x) => (SRAconst (NEG <t> x) [31])
172
173 // float-int conversion
174 (Cvt32to(32|64)F ...) => (MOVW(F|D) ...)
175 (Cvt(32|64)Fto32 ...) => (TRUNC(F|D)W ...)
176 (Cvt32Fto64F ...) => (MOVFD ...)
177 (Cvt64Fto32F ...) => (MOVDF ...)
178
179 (CvtBoolToUint8 ...) => (Copy ...)
180
181 (Round(32|64)F ...) => (Copy ...)
182
183 // comparisons
184 (Eq8 x y) => (SGTUconst [1] (XOR (ZeroExt8to32 x) (ZeroExt8to32 y)))
185 (Eq16 x y) => (SGTUconst [1] (XOR (ZeroExt16to32 x) (ZeroExt16to32 y)))
186 (Eq32 x y) => (SGTUconst [1] (XOR x y))
187 (EqPtr x y) => (SGTUconst [1] (XOR x y))
188 (Eq(32|64)F x y) => (FPFlagTrue (CMPEQ(F|D) x y))
189
190 (Neq8 x y) => (SGTU (XOR (ZeroExt8to32 x) (ZeroExt8to32 y)) (MOVWconst [0]))
191 (Neq16 x y) => (SGTU (XOR (ZeroExt16to32 x) (ZeroExt16to32 y)) (MOVWconst [0]))
192 (Neq32 x y) => (SGTU (XOR x y) (MOVWconst [0]))
193 (NeqPtr x y) => (SGTU (XOR x y) (MOVWconst [0]))
194 (Neq(32|64)F x y) => (FPFlagFalse (CMPEQ(F|D) x y))
195
196 (Less8 x y) => (SGT (SignExt8to32 y) (SignExt8to32 x))
197 (Less16 x y) => (SGT (SignExt16to32 y) (SignExt16to32 x))
198 (Less32 x y) => (SGT y x)
199 (Less(32|64)F x y) => (FPFlagTrue (CMPGT(F|D) y x)) // reverse operands to work around NaN
200
201 (Less8U x y) => (SGTU (ZeroExt8to32 y) (ZeroExt8to32 x))
202 (Less16U x y) => (SGTU (ZeroExt16to32 y) (ZeroExt16to32 x))
203 (Less32U x y) => (SGTU y x)
204
205 (Leq8 x y) => (XORconst [1] (SGT (SignExt8to32 x) (SignExt8to32 y)))
206 (Leq16 x y) => (XORconst [1] (SGT (SignExt16to32 x) (SignExt16to32 y)))
207 (Leq32 x y) => (XORconst [1] (SGT x y))
208 (Leq(32|64)F x y) => (FPFlagTrue (CMPGE(F|D) y x)) // reverse operands to work around NaN
209
210 (Leq8U x y) => (XORconst [1] (SGTU (ZeroExt8to32 x) (ZeroExt8to32 y)))
211 (Leq16U x y) => (XORconst [1] (SGTU (ZeroExt16to32 x) (ZeroExt16to32 y)))
212 (Leq32U x y) => (XORconst [1] (SGTU x y))
213
214 (OffPtr [off] ptr:(SP)) => (MOVWaddr [int32(off)] ptr)
215 (OffPtr [off] ptr) => (ADDconst [int32(off)] ptr)
216
217 (Addr {sym} base) => (MOVWaddr {sym} base)
218 (LocalAddr <t> {sym} base mem) && t.Elem().HasPointers() => (MOVWaddr {sym} (SPanchored base mem))
219 (LocalAddr <t> {sym} base _) && !t.Elem().HasPointers() => (MOVWaddr {sym} base)
220
221 // loads
222 (Load <t> ptr mem) && t.IsBoolean() => (MOVBUload ptr mem)
223 (Load <t> ptr mem) && (is8BitInt(t) && t.IsSigned()) => (MOVBload ptr mem)
224 (Load <t> ptr mem) && (is8BitInt(t) && !t.IsSigned()) => (MOVBUload ptr mem)
225 (Load <t> ptr mem) && (is16BitInt(t) && t.IsSigned()) => (MOVHload ptr mem)
226 (Load <t> ptr mem) && (is16BitInt(t) && !t.IsSigned()) => (MOVHUload ptr mem)
227 (Load <t> ptr mem) && (is32BitInt(t) || isPtr(t)) => (MOVWload ptr mem)
228 (Load <t> ptr mem) && is32BitFloat(t) => (MOVFload ptr mem)
229 (Load <t> ptr mem) && is64BitFloat(t) => (MOVDload ptr mem)
230
231 // stores
232 (Store {t} ptr val mem) && t.Size() == 1 => (MOVBstore ptr val mem)
233 (Store {t} ptr val mem) && t.Size() == 2 => (MOVHstore ptr val mem)
234 (Store {t} ptr val mem) && t.Size() == 4 && !t.IsFloat() => (MOVWstore ptr val mem)
235 (Store {t} ptr val mem) && t.Size() == 4 && t.IsFloat() => (MOVFstore ptr val mem)
236 (Store {t} ptr val mem) && t.Size() == 8 && t.IsFloat() => (MOVDstore ptr val mem)
237
238 // float <=> int register moves, with no conversion.
239 // These come up when compiling math.{Float32bits, Float32frombits}.
240 (MOVWload [off] {sym} ptr (MOVFstore [off] {sym} ptr val _)) => (MOVWfpgp val)
241 (MOVFload [off] {sym} ptr (MOVWstore [off] {sym} ptr val _)) => (MOVWgpfp val)
242
243 // Similarly for stores, if we see a store after FPR <=> GPR move, then redirect store to use the other register set.
244 (MOVWstore [off] {sym} ptr (MOVWfpgp val) mem) => (MOVFstore [off] {sym} ptr val mem)
245 (MOVFstore [off] {sym} ptr (MOVWgpfp val) mem) => (MOVWstore [off] {sym} ptr val mem)
246
247 // zero instructions
248 (Zero [0] _ mem) => mem
249 (Zero [1] ptr mem) => (MOVBstore ptr (MOVWconst [0]) mem)
250 (Zero [2] {t} ptr mem) && t.Alignment()%2 == 0 =>
251 (MOVHstore ptr (MOVWconst [0]) mem)
252 (Zero [2] ptr mem) =>
253 (MOVBstore [1] ptr (MOVWconst [0])
254 (MOVBstore [0] ptr (MOVWconst [0]) mem))
255 (Zero [4] {t} ptr mem) && t.Alignment()%4 == 0 =>
256 (MOVWstore ptr (MOVWconst [0]) mem)
257 (Zero [4] {t} ptr mem) && t.Alignment()%2 == 0 =>
258 (MOVHstore [2] ptr (MOVWconst [0])
259 (MOVHstore [0] ptr (MOVWconst [0]) mem))
260 (Zero [4] ptr mem) =>
261 (MOVBstore [3] ptr (MOVWconst [0])
262 (MOVBstore [2] ptr (MOVWconst [0])
263 (MOVBstore [1] ptr (MOVWconst [0])
264 (MOVBstore [0] ptr (MOVWconst [0]) mem))))
265 (Zero [3] ptr mem) =>
266 (MOVBstore [2] ptr (MOVWconst [0])
267 (MOVBstore [1] ptr (MOVWconst [0])
268 (MOVBstore [0] ptr (MOVWconst [0]) mem)))
269 (Zero [6] {t} ptr mem) && t.Alignment()%2 == 0 =>
270 (MOVHstore [4] ptr (MOVWconst [0])
271 (MOVHstore [2] ptr (MOVWconst [0])
272 (MOVHstore [0] ptr (MOVWconst [0]) mem)))
273 (Zero [8] {t} ptr mem) && t.Alignment()%4 == 0 =>
274 (MOVWstore [4] ptr (MOVWconst [0])
275 (MOVWstore [0] ptr (MOVWconst [0]) mem))
276 (Zero [12] {t} ptr mem) && t.Alignment()%4 == 0 =>
277 (MOVWstore [8] ptr (MOVWconst [0])
278 (MOVWstore [4] ptr (MOVWconst [0])
279 (MOVWstore [0] ptr (MOVWconst [0]) mem)))
280 (Zero [16] {t} ptr mem) && t.Alignment()%4 == 0 =>
281 (MOVWstore [12] ptr (MOVWconst [0])
282 (MOVWstore [8] ptr (MOVWconst [0])
283 (MOVWstore [4] ptr (MOVWconst [0])
284 (MOVWstore [0] ptr (MOVWconst [0]) mem))))
285
286 // large or unaligned zeroing uses a loop
287 (Zero [s] {t} ptr mem)
288 && (s > 16 || t.Alignment()%4 != 0) =>
289 (LoweredZero [int32(t.Alignment())]
290 ptr
291 (ADDconst <ptr.Type> ptr [int32(s-moveSize(t.Alignment(), config))])
292 mem)
293
294 // moves
295 (Move [0] _ _ mem) => mem
296 (Move [1] dst src mem) => (MOVBstore dst (MOVBUload src mem) mem)
297 (Move [2] {t} dst src mem) && t.Alignment()%2 == 0 =>
298 (MOVHstore dst (MOVHUload src mem) mem)
299 (Move [2] dst src mem) =>
300 (MOVBstore [1] dst (MOVBUload [1] src mem)
301 (MOVBstore dst (MOVBUload src mem) mem))
302 (Move [4] {t} dst src mem) && t.Alignment()%4 == 0 =>
303 (MOVWstore dst (MOVWload src mem) mem)
304 (Move [4] {t} dst src mem) && t.Alignment()%2 == 0 =>
305 (MOVHstore [2] dst (MOVHUload [2] src mem)
306 (MOVHstore dst (MOVHUload src mem) mem))
307 (Move [4] dst src mem) =>
308 (MOVBstore [3] dst (MOVBUload [3] src mem)
309 (MOVBstore [2] dst (MOVBUload [2] src mem)
310 (MOVBstore [1] dst (MOVBUload [1] src mem)
311 (MOVBstore dst (MOVBUload src mem) mem))))
312 (Move [3] dst src mem) =>
313 (MOVBstore [2] dst (MOVBUload [2] src mem)
314 (MOVBstore [1] dst (MOVBUload [1] src mem)
315 (MOVBstore dst (MOVBUload src mem) mem)))
316 (Move [8] {t} dst src mem) && t.Alignment()%4 == 0 =>
317 (MOVWstore [4] dst (MOVWload [4] src mem)
318 (MOVWstore dst (MOVWload src mem) mem))
319 (Move [8] {t} dst src mem) && t.Alignment()%2 == 0 =>
320 (MOVHstore [6] dst (MOVHload [6] src mem)
321 (MOVHstore [4] dst (MOVHload [4] src mem)
322 (MOVHstore [2] dst (MOVHload [2] src mem)
323 (MOVHstore dst (MOVHload src mem) mem))))
324 (Move [6] {t} dst src mem) && t.Alignment()%2 == 0 =>
325 (MOVHstore [4] dst (MOVHload [4] src mem)
326 (MOVHstore [2] dst (MOVHload [2] src mem)
327 (MOVHstore dst (MOVHload src mem) mem)))
328 (Move [12] {t} dst src mem) && t.Alignment()%4 == 0 =>
329 (MOVWstore [8] dst (MOVWload [8] src mem)
330 (MOVWstore [4] dst (MOVWload [4] src mem)
331 (MOVWstore dst (MOVWload src mem) mem)))
332 (Move [16] {t} dst src mem) && t.Alignment()%4 == 0 =>
333 (MOVWstore [12] dst (MOVWload [12] src mem)
334 (MOVWstore [8] dst (MOVWload [8] src mem)
335 (MOVWstore [4] dst (MOVWload [4] src mem)
336 (MOVWstore dst (MOVWload src mem) mem))))
337
338
339 // large or unaligned move uses a loop
340 (Move [s] {t} dst src mem)
341 && (s > 16 && logLargeCopy(v, s) || t.Alignment()%4 != 0) =>
342 (LoweredMove [int32(t.Alignment())]
343 dst
344 src
345 (ADDconst <src.Type> src [int32(s-moveSize(t.Alignment(), config))])
346 mem)
347
348 // calls
349 (StaticCall ...) => (CALLstatic ...)
350 (ClosureCall ...) => (CALLclosure ...)
351 (InterCall ...) => (CALLinter ...)
352 (TailCall ...) => (CALLtail ...)
353
354 // atomic intrinsics
355 (AtomicLoad(8|32) ...) => (LoweredAtomicLoad(8|32) ...)
356 (AtomicLoadPtr ...) => (LoweredAtomicLoad32 ...)
357
358 (AtomicStore(8|32) ...) => (LoweredAtomicStore(8|32) ...)
359 (AtomicStorePtrNoWB ...) => (LoweredAtomicStore32 ...)
360
361 (AtomicExchange32 ...) => (LoweredAtomicExchange ...)
362 (AtomicAdd32 ...) => (LoweredAtomicAdd ...)
363
364 (AtomicCompareAndSwap32 ...) => (LoweredAtomicCas ...)
365
366 // AtomicOr8(ptr,val) => LoweredAtomicOr(ptr&^3,uint32(val) << ((ptr & 3) * 8))
367 (AtomicOr8 ptr val mem) && !config.BigEndian =>
368 (LoweredAtomicOr (AND <typ.UInt32Ptr> (MOVWconst [^3]) ptr)
369 (SLL <typ.UInt32> (ZeroExt8to32 val)
370 (SLLconst <typ.UInt32> [3]
371 (ANDconst <typ.UInt32> [3] ptr))) mem)
372
373 // AtomicAnd8(ptr,val) => LoweredAtomicAnd(ptr&^3,(uint32(val) << ((ptr & 3) * 8)) | ^(uint32(0xFF) << ((ptr & 3) * 8))))
374 (AtomicAnd8 ptr val mem) && !config.BigEndian =>
375 (LoweredAtomicAnd (AND <typ.UInt32Ptr> (MOVWconst [^3]) ptr)
376 (OR <typ.UInt32> (SLL <typ.UInt32> (ZeroExt8to32 val)
377 (SLLconst <typ.UInt32> [3]
378 (ANDconst <typ.UInt32> [3] ptr)))
379 (NORconst [0] <typ.UInt32> (SLL <typ.UInt32>
380 (MOVWconst [0xff]) (SLLconst <typ.UInt32> [3]
381 (ANDconst <typ.UInt32> [3] ptr))))) mem)
382
383 // AtomicOr8(ptr,val) => LoweredAtomicOr(ptr&^3,uint32(val) << (((ptr^3) & 3) * 8))
384 (AtomicOr8 ptr val mem) && config.BigEndian =>
385 (LoweredAtomicOr (AND <typ.UInt32Ptr> (MOVWconst [^3]) ptr)
386 (SLL <typ.UInt32> (ZeroExt8to32 val)
387 (SLLconst <typ.UInt32> [3]
388 (ANDconst <typ.UInt32> [3]
389 (XORconst <typ.UInt32> [3] ptr)))) mem)
390
391 // AtomicAnd8(ptr,val) => LoweredAtomicAnd(ptr&^3,(uint32(val) << (((ptr^3) & 3) * 8)) | ^(uint32(0xFF) << (((ptr^3) & 3) * 8))))
392 (AtomicAnd8 ptr val mem) && config.BigEndian =>
393 (LoweredAtomicAnd (AND <typ.UInt32Ptr> (MOVWconst [^3]) ptr)
394 (OR <typ.UInt32> (SLL <typ.UInt32> (ZeroExt8to32 val)
395 (SLLconst <typ.UInt32> [3]
396 (ANDconst <typ.UInt32> [3]
397 (XORconst <typ.UInt32> [3] ptr))))
398 (NORconst [0] <typ.UInt32> (SLL <typ.UInt32>
399 (MOVWconst [0xff]) (SLLconst <typ.UInt32> [3]
400 (ANDconst <typ.UInt32> [3]
401 (XORconst <typ.UInt32> [3] ptr)))))) mem)
402
403 (AtomicAnd32 ...) => (LoweredAtomicAnd ...)
404 (AtomicOr32 ...) => (LoweredAtomicOr ...)
405
406
407 // checks
408 (NilCheck ...) => (LoweredNilCheck ...)
409 (IsNonNil ptr) => (SGTU ptr (MOVWconst [0]))
410 (IsInBounds idx len) => (SGTU len idx)
411 (IsSliceInBounds idx len) => (XORconst [1] (SGTU idx len))
412
413 // pseudo-ops
414 (GetClosurePtr ...) => (LoweredGetClosurePtr ...)
415 (GetCallerSP ...) => (LoweredGetCallerSP ...)
416 (GetCallerPC ...) => (LoweredGetCallerPC ...)
417
418 (If cond yes no) => (NE cond yes no)
419
420 // Write barrier.
421 (WB ...) => (LoweredWB ...)
422
423 // Publication barrier as intrinsic
424 (PubBarrier ...) => (LoweredPubBarrier ...)
425
426 (PanicBounds [kind] x y mem) && boundsABI(kind) == 0 => (LoweredPanicBoundsA [kind] x y mem)
427 (PanicBounds [kind] x y mem) && boundsABI(kind) == 1 => (LoweredPanicBoundsB [kind] x y mem)
428 (PanicBounds [kind] x y mem) && boundsABI(kind) == 2 => (LoweredPanicBoundsC [kind] x y mem)
429
430 (PanicExtend [kind] hi lo y mem) && boundsABI(kind) == 0 => (LoweredPanicExtendA [kind] hi lo y mem)
431 (PanicExtend [kind] hi lo y mem) && boundsABI(kind) == 1 => (LoweredPanicExtendB [kind] hi lo y mem)
432 (PanicExtend [kind] hi lo y mem) && boundsABI(kind) == 2 => (LoweredPanicExtendC [kind] hi lo y mem)
433
434 // Optimizations
435
436 // Absorb boolean tests into block
437 (NE (FPFlagTrue cmp) yes no) => (FPT cmp yes no)
438 (NE (FPFlagFalse cmp) yes no) => (FPF cmp yes no)
439 (EQ (FPFlagTrue cmp) yes no) => (FPF cmp yes no)
440 (EQ (FPFlagFalse cmp) yes no) => (FPT cmp yes no)
441 (NE (XORconst [1] cmp:(SGT _ _)) yes no) => (EQ cmp yes no)
442 (NE (XORconst [1] cmp:(SGTU _ _)) yes no) => (EQ cmp yes no)
443 (NE (XORconst [1] cmp:(SGTconst _)) yes no) => (EQ cmp yes no)
444 (NE (XORconst [1] cmp:(SGTUconst _)) yes no) => (EQ cmp yes no)
445 (NE (XORconst [1] cmp:(SGTzero _)) yes no) => (EQ cmp yes no)
446 (NE (XORconst [1] cmp:(SGTUzero _)) yes no) => (EQ cmp yes no)
447 (EQ (XORconst [1] cmp:(SGT _ _)) yes no) => (NE cmp yes no)
448 (EQ (XORconst [1] cmp:(SGTU _ _)) yes no) => (NE cmp yes no)
449 (EQ (XORconst [1] cmp:(SGTconst _)) yes no) => (NE cmp yes no)
450 (EQ (XORconst [1] cmp:(SGTUconst _)) yes no) => (NE cmp yes no)
451 (EQ (XORconst [1] cmp:(SGTzero _)) yes no) => (NE cmp yes no)
452 (EQ (XORconst [1] cmp:(SGTUzero _)) yes no) => (NE cmp yes no)
453 (NE (SGTUconst [1] x) yes no) => (EQ x yes no)
454 (EQ (SGTUconst [1] x) yes no) => (NE x yes no)
455 (NE (SGTUzero x) yes no) => (NE x yes no)
456 (EQ (SGTUzero x) yes no) => (EQ x yes no)
457 (NE (SGTconst [0] x) yes no) => (LTZ x yes no)
458 (EQ (SGTconst [0] x) yes no) => (GEZ x yes no)
459 (NE (SGTzero x) yes no) => (GTZ x yes no)
460 (EQ (SGTzero x) yes no) => (LEZ x yes no)
461
462 // fold offset into address
463 (ADDconst [off1] (MOVWaddr [off2] {sym} ptr)) => (MOVWaddr [off1+off2] {sym} ptr)
464
465 // fold address into load/store
466 (MOVBload [off1] {sym} x:(ADDconst [off2] ptr) mem) && (is16Bit(int64(off1+off2)) || x.Uses == 1) => (MOVBload [off1+off2] {sym} ptr mem)
467 (MOVBUload [off1] {sym} x:(ADDconst [off2] ptr) mem) && (is16Bit(int64(off1+off2)) || x.Uses == 1) => (MOVBUload [off1+off2] {sym} ptr mem)
468 (MOVHload [off1] {sym} x:(ADDconst [off2] ptr) mem) && (is16Bit(int64(off1+off2)) || x.Uses == 1) => (MOVHload [off1+off2] {sym} ptr mem)
469 (MOVHUload [off1] {sym} x:(ADDconst [off2] ptr) mem) && (is16Bit(int64(off1+off2)) || x.Uses == 1) => (MOVHUload [off1+off2] {sym} ptr mem)
470 (MOVWload [off1] {sym} x:(ADDconst [off2] ptr) mem) && (is16Bit(int64(off1+off2)) || x.Uses == 1) => (MOVWload [off1+off2] {sym} ptr mem)
471 (MOVFload [off1] {sym} x:(ADDconst [off2] ptr) mem) && (is16Bit(int64(off1+off2)) || x.Uses == 1) => (MOVFload [off1+off2] {sym} ptr mem)
472 (MOVDload [off1] {sym} x:(ADDconst [off2] ptr) mem) && (is16Bit(int64(off1+off2)) || x.Uses == 1) => (MOVDload [off1+off2] {sym} ptr mem)
473
474 (MOVBstore [off1] {sym} x:(ADDconst [off2] ptr) val mem) && (is16Bit(int64(off1+off2)) || x.Uses == 1) => (MOVBstore [off1+off2] {sym} ptr val mem)
475 (MOVHstore [off1] {sym} x:(ADDconst [off2] ptr) val mem) && (is16Bit(int64(off1+off2)) || x.Uses == 1) => (MOVHstore [off1+off2] {sym} ptr val mem)
476 (MOVWstore [off1] {sym} x:(ADDconst [off2] ptr) val mem) && (is16Bit(int64(off1+off2)) || x.Uses == 1) => (MOVWstore [off1+off2] {sym} ptr val mem)
477 (MOVFstore [off1] {sym} x:(ADDconst [off2] ptr) val mem) && (is16Bit(int64(off1+off2)) || x.Uses == 1) => (MOVFstore [off1+off2] {sym} ptr val mem)
478 (MOVDstore [off1] {sym} x:(ADDconst [off2] ptr) val mem) && (is16Bit(int64(off1+off2)) || x.Uses == 1) => (MOVDstore [off1+off2] {sym} ptr val mem)
479
480 (MOVBstorezero [off1] {sym} x:(ADDconst [off2] ptr) mem) && (is16Bit(int64(off1+off2)) || x.Uses == 1) => (MOVBstorezero [off1+off2] {sym} ptr mem)
481 (MOVHstorezero [off1] {sym} x:(ADDconst [off2] ptr) mem) && (is16Bit(int64(off1+off2)) || x.Uses == 1) => (MOVHstorezero [off1+off2] {sym} ptr mem)
482 (MOVWstorezero [off1] {sym} x:(ADDconst [off2] ptr) mem) && (is16Bit(int64(off1+off2)) || x.Uses == 1) => (MOVWstorezero [off1+off2] {sym} ptr mem)
483
484 (MOVBload [off1] {sym1} (MOVWaddr [off2] {sym2} ptr) mem) && canMergeSym(sym1,sym2) =>
485 (MOVBload [off1+off2] {mergeSym(sym1,sym2)} ptr mem)
486 (MOVBUload [off1] {sym1} (MOVWaddr [off2] {sym2} ptr) mem) && canMergeSym(sym1,sym2) =>
487 (MOVBUload [off1+off2] {mergeSym(sym1,sym2)} ptr mem)
488 (MOVHload [off1] {sym1} (MOVWaddr [off2] {sym2} ptr) mem) && canMergeSym(sym1,sym2) =>
489 (MOVHload [off1+off2] {mergeSym(sym1,sym2)} ptr mem)
490 (MOVHUload [off1] {sym1} (MOVWaddr [off2] {sym2} ptr) mem) && canMergeSym(sym1,sym2) =>
491 (MOVHUload [off1+off2] {mergeSym(sym1,sym2)} ptr mem)
492 (MOVWload [off1] {sym1} (MOVWaddr [off2] {sym2} ptr) mem) && canMergeSym(sym1,sym2) =>
493 (MOVWload [off1+off2] {mergeSym(sym1,sym2)} ptr mem)
494 (MOVFload [off1] {sym1} (MOVWaddr [off2] {sym2} ptr) mem) && canMergeSym(sym1,sym2) =>
495 (MOVFload [off1+off2] {mergeSym(sym1,sym2)} ptr mem)
496 (MOVDload [off1] {sym1} (MOVWaddr [off2] {sym2} ptr) mem) && canMergeSym(sym1,sym2) =>
497 (MOVDload [off1+off2] {mergeSym(sym1,sym2)} ptr mem)
498
499 (MOVBstore [off1] {sym1} (MOVWaddr [off2] {sym2} ptr) val mem) && canMergeSym(sym1,sym2) =>
500 (MOVBstore [off1+off2] {mergeSym(sym1,sym2)} ptr val mem)
501 (MOVHstore [off1] {sym1} (MOVWaddr [off2] {sym2} ptr) val mem) && canMergeSym(sym1,sym2) =>
502 (MOVHstore [off1+off2] {mergeSym(sym1,sym2)} ptr val mem)
503 (MOVWstore [off1] {sym1} (MOVWaddr [off2] {sym2} ptr) val mem) && canMergeSym(sym1,sym2) =>
504 (MOVWstore [off1+off2] {mergeSym(sym1,sym2)} ptr val mem)
505 (MOVFstore [off1] {sym1} (MOVWaddr [off2] {sym2} ptr) val mem) && canMergeSym(sym1,sym2) =>
506 (MOVFstore [off1+off2] {mergeSym(sym1,sym2)} ptr val mem)
507 (MOVDstore [off1] {sym1} (MOVWaddr [off2] {sym2} ptr) val mem) && canMergeSym(sym1,sym2) =>
508 (MOVDstore [off1+off2] {mergeSym(sym1,sym2)} ptr val mem)
509 (MOVBstorezero [off1] {sym1} (MOVWaddr [off2] {sym2} ptr) mem) && canMergeSym(sym1,sym2) =>
510 (MOVBstorezero [off1+off2] {mergeSym(sym1,sym2)} ptr mem)
511 (MOVHstorezero [off1] {sym1} (MOVWaddr [off2] {sym2} ptr) mem) && canMergeSym(sym1,sym2) =>
512 (MOVHstorezero [off1+off2] {mergeSym(sym1,sym2)} ptr mem)
513 (MOVWstorezero [off1] {sym1} (MOVWaddr [off2] {sym2} ptr) mem) && canMergeSym(sym1,sym2) =>
514 (MOVWstorezero [off1+off2] {mergeSym(sym1,sym2)} ptr mem)
515
516 // replace load from same location as preceding store with zero/sign extension (or copy in case of full width)
517 (MOVBload [off] {sym} ptr (MOVBstore [off2] {sym2} ptr2 x _)) && sym == sym2 && off == off2 && isSamePtr(ptr, ptr2) => (MOVBreg x)
518 (MOVBUload [off] {sym} ptr (MOVBstore [off2] {sym2} ptr2 x _)) && sym == sym2 && off == off2 && isSamePtr(ptr, ptr2) => (MOVBUreg x)
519 (MOVHload [off] {sym} ptr (MOVHstore [off2] {sym2} ptr2 x _)) && sym == sym2 && off == off2 && isSamePtr(ptr, ptr2) => (MOVHreg x)
520 (MOVHUload [off] {sym} ptr (MOVHstore [off2] {sym2} ptr2 x _)) && sym == sym2 && off == off2 && isSamePtr(ptr, ptr2) => (MOVHUreg x)
521 (MOVWload [off] {sym} ptr (MOVWstore [off2] {sym2} ptr2 x _)) && sym == sym2 && off == off2 && isSamePtr(ptr, ptr2) => x
522 (MOVFload [off] {sym} ptr (MOVFstore [off2] {sym2} ptr2 x _)) && sym == sym2 && off == off2 && isSamePtr(ptr, ptr2) => x
523 (MOVDload [off] {sym} ptr (MOVDstore [off2] {sym2} ptr2 x _)) && sym == sym2 && off == off2 && isSamePtr(ptr, ptr2) => x
524
525 // store zero
526 (MOVBstore [off] {sym} ptr (MOVWconst [0]) mem) => (MOVBstorezero [off] {sym} ptr mem)
527 (MOVHstore [off] {sym} ptr (MOVWconst [0]) mem) => (MOVHstorezero [off] {sym} ptr mem)
528 (MOVWstore [off] {sym} ptr (MOVWconst [0]) mem) => (MOVWstorezero [off] {sym} ptr mem)
529
530 // don't extend after proper load
531 (MOVBreg x:(MOVBload _ _)) => (MOVWreg x)
532 (MOVBUreg x:(MOVBUload _ _)) => (MOVWreg x)
533 (MOVHreg x:(MOVBload _ _)) => (MOVWreg x)
534 (MOVHreg x:(MOVBUload _ _)) => (MOVWreg x)
535 (MOVHreg x:(MOVHload _ _)) => (MOVWreg x)
536 (MOVHUreg x:(MOVBUload _ _)) => (MOVWreg x)
537 (MOVHUreg x:(MOVHUload _ _)) => (MOVWreg x)
538
539 // fold double extensions
540 (MOVBreg x:(MOVBreg _)) => (MOVWreg x)
541 (MOVBUreg x:(MOVBUreg _)) => (MOVWreg x)
542 (MOVHreg x:(MOVBreg _)) => (MOVWreg x)
543 (MOVHreg x:(MOVBUreg _)) => (MOVWreg x)
544 (MOVHreg x:(MOVHreg _)) => (MOVWreg x)
545 (MOVHUreg x:(MOVBUreg _)) => (MOVWreg x)
546 (MOVHUreg x:(MOVHUreg _)) => (MOVWreg x)
547
548 // sign extended loads
549 // Note: The combined instruction must end up in the same block
550 // as the original load. If not, we end up making a value with
551 // memory type live in two different blocks, which can lead to
552 // multiple memory values alive simultaneously.
553 // Make sure we don't combine these ops if the load has another use.
554 // This prevents a single load from being split into multiple loads
555 // which then might return different values. See test/atomicload.go.
556 (MOVBreg <t> x:(MOVBUload [off] {sym} ptr mem)) && x.Uses == 1 && clobber(x) => @x.Block (MOVBload <t> [off] {sym} ptr mem)
557 (MOVBUreg <t> x:(MOVBload [off] {sym} ptr mem)) && x.Uses == 1 && clobber(x) => @x.Block (MOVBUload <t> [off] {sym} ptr mem)
558 (MOVHreg <t> x:(MOVHUload [off] {sym} ptr mem)) && x.Uses == 1 && clobber(x) => @x.Block (MOVHload <t> [off] {sym} ptr mem)
559 (MOVHUreg <t> x:(MOVHload [off] {sym} ptr mem)) && x.Uses == 1 && clobber(x) => @x.Block (MOVHUload <t> [off] {sym} ptr mem)
560
561 // fold extensions and ANDs together
562 (MOVBUreg (ANDconst [c] x)) => (ANDconst [c&0xff] x)
563 (MOVHUreg (ANDconst [c] x)) => (ANDconst [c&0xffff] x)
564 (MOVBreg (ANDconst [c] x)) && c & 0x80 == 0 => (ANDconst [c&0x7f] x)
565 (MOVHreg (ANDconst [c] x)) && c & 0x8000 == 0 => (ANDconst [c&0x7fff] x)
566
567 // don't extend before store
568 (MOVBstore [off] {sym} ptr (MOVBreg x) mem) => (MOVBstore [off] {sym} ptr x mem)
569 (MOVBstore [off] {sym} ptr (MOVBUreg x) mem) => (MOVBstore [off] {sym} ptr x mem)
570 (MOVBstore [off] {sym} ptr (MOVHreg x) mem) => (MOVBstore [off] {sym} ptr x mem)
571 (MOVBstore [off] {sym} ptr (MOVHUreg x) mem) => (MOVBstore [off] {sym} ptr x mem)
572 (MOVBstore [off] {sym} ptr (MOVWreg x) mem) => (MOVBstore [off] {sym} ptr x mem)
573 (MOVHstore [off] {sym} ptr (MOVHreg x) mem) => (MOVHstore [off] {sym} ptr x mem)
574 (MOVHstore [off] {sym} ptr (MOVHUreg x) mem) => (MOVHstore [off] {sym} ptr x mem)
575 (MOVHstore [off] {sym} ptr (MOVWreg x) mem) => (MOVHstore [off] {sym} ptr x mem)
576 (MOVWstore [off] {sym} ptr (MOVWreg x) mem) => (MOVWstore [off] {sym} ptr x mem)
577
578 // if a register move has only 1 use, just use the same register without emitting instruction
579 // MOVWnop doesn't emit instruction, only for ensuring the type.
580 (MOVWreg x) && x.Uses == 1 => (MOVWnop x)
581
582 // TODO: we should be able to get rid of MOVWnop all together.
583 // But for now, this is enough to get rid of lots of them.
584 (MOVWnop (MOVWconst [c])) => (MOVWconst [c])
585
586 // fold constant into arithmetic ops
587 (ADD x (MOVWconst <t> [c])) && !t.IsPtr() => (ADDconst [c] x)
588 (SUB x (MOVWconst [c])) => (SUBconst [c] x)
589 (AND x (MOVWconst [c])) => (ANDconst [c] x)
590 (OR x (MOVWconst [c])) => (ORconst [c] x)
591 (XOR x (MOVWconst [c])) => (XORconst [c] x)
592 (NOR x (MOVWconst [c])) => (NORconst [c] x)
593
594 (SLL x (MOVWconst [c])) => (SLLconst x [c&31])
595 (SRL x (MOVWconst [c])) => (SRLconst x [c&31])
596 (SRA x (MOVWconst [c])) => (SRAconst x [c&31])
597
598 (SGT (MOVWconst [c]) x) => (SGTconst [c] x)
599 (SGTU (MOVWconst [c]) x) => (SGTUconst [c] x)
600 (SGT x (MOVWconst [0])) => (SGTzero x)
601 (SGTU x (MOVWconst [0])) => (SGTUzero x)
602
603 // mul with constant
604 (Select1 (MULTU (MOVWconst [0]) _ )) => (MOVWconst [0])
605 (Select0 (MULTU (MOVWconst [0]) _ )) => (MOVWconst [0])
606 (Select1 (MULTU (MOVWconst [1]) x )) => x
607 (Select0 (MULTU (MOVWconst [1]) _ )) => (MOVWconst [0])
608 (Select1 (MULTU (MOVWconst [-1]) x )) => (NEG <x.Type> x)
609 (Select0 (MULTU (MOVWconst [-1]) x )) => (CMOVZ (ADDconst <x.Type> [-1] x) (MOVWconst [0]) x)
610 (Select1 (MULTU (MOVWconst [c]) x )) && isPowerOfTwo(int64(uint32(c))) => (SLLconst [int32(log2uint32(int64(c)))] x)
611 (Select0 (MULTU (MOVWconst [c]) x )) && isPowerOfTwo(int64(uint32(c))) => (SRLconst [int32(32-log2uint32(int64(c)))] x)
612
613 (MUL (MOVWconst [0]) _ ) => (MOVWconst [0])
614 (MUL (MOVWconst [1]) x ) => x
615 (MUL (MOVWconst [-1]) x ) => (NEG x)
616 (MUL (MOVWconst [c]) x ) && isPowerOfTwo(int64(uint32(c))) => (SLLconst [int32(log2uint32(int64(c)))] x)
617
618 // generic simplifications
619 (ADD x (NEG y)) => (SUB x y)
620 (SUB x (NEG y)) => (ADD x y)
621 (SUB x x) => (MOVWconst [0])
622 (SUB (MOVWconst [0]) x) => (NEG x)
623 (AND x x) => x
624 (OR x x) => x
625 (XOR x x) => (MOVWconst [0])
626 (NEG (SUB x y)) => (SUB y x)
627 (NEG (NEG x)) => x
628
629 // miscellaneous patterns generated by dec64
630 (AND (SGTUconst [1] x) (SGTUconst [1] y)) => (SGTUconst [1] (OR <x.Type> x y))
631 (OR (SGTUzero x) (SGTUzero y)) => (SGTUzero (OR <x.Type> x y))
632
633 // remove redundant *const ops
634 (ADDconst [0] x) => x
635 (SUBconst [0] x) => x
636 (ANDconst [0] _) => (MOVWconst [0])
637 (ANDconst [-1] x) => x
638 (ORconst [0] x) => x
639 (ORconst [-1] _) => (MOVWconst [-1])
640 (XORconst [0] x) => x
641 (XORconst [-1] x) => (NORconst [0] x)
642
643 // generic constant folding
644 (ADDconst [c] (MOVWconst [d])) => (MOVWconst [int32(c+d)])
645 (ADDconst [c] (ADDconst [d] x)) => (ADDconst [c+d] x)
646 (ADDconst [c] (SUBconst [d] x)) => (ADDconst [c-d] x)
647 (SUBconst [c] (MOVWconst [d])) => (MOVWconst [d-c])
648 (SUBconst [c] (SUBconst [d] x)) => (ADDconst [-c-d] x)
649 (SUBconst [c] (ADDconst [d] x)) => (ADDconst [-c+d] x)
650 (SLLconst [c] (MOVWconst [d])) => (MOVWconst [d<<uint32(c)])
651 (SRLconst [c] (MOVWconst [d])) => (MOVWconst [int32(uint32(d)>>uint32(c))])
652 (SRAconst [c] (MOVWconst [d])) => (MOVWconst [d>>uint32(c)])
653 (MUL (MOVWconst [c]) (MOVWconst [d])) => (MOVWconst [c*d])
654 (Select1 (MULTU (MOVWconst [c]) (MOVWconst [d]))) => (MOVWconst [int32(uint32(c)*uint32(d))])
655 (Select0 (MULTU (MOVWconst [c]) (MOVWconst [d]))) => (MOVWconst [int32((int64(uint32(c))*int64(uint32(d)))>>32)])
656 (Select1 (DIV (MOVWconst [c]) (MOVWconst [d]))) && d != 0 => (MOVWconst [c/d])
657 (Select1 (DIVU (MOVWconst [c]) (MOVWconst [d]))) && d != 0 => (MOVWconst [int32(uint32(c)/uint32(d))])
658 (Select0 (DIV (MOVWconst [c]) (MOVWconst [d]))) && d != 0 => (MOVWconst [c%d])
659 (Select0 (DIVU (MOVWconst [c]) (MOVWconst [d]))) && d != 0 => (MOVWconst [int32(uint32(c)%uint32(d))])
660 (ANDconst [c] (MOVWconst [d])) => (MOVWconst [c&d])
661 (ANDconst [c] (ANDconst [d] x)) => (ANDconst [c&d] x)
662 (ORconst [c] (MOVWconst [d])) => (MOVWconst [c|d])
663 (ORconst [c] (ORconst [d] x)) => (ORconst [c|d] x)
664 (XORconst [c] (MOVWconst [d])) => (MOVWconst [c^d])
665 (XORconst [c] (XORconst [d] x)) => (XORconst [c^d] x)
666 (NORconst [c] (MOVWconst [d])) => (MOVWconst [^(c|d)])
667 (NEG (MOVWconst [c])) => (MOVWconst [-c])
668 (MOVBreg (MOVWconst [c])) => (MOVWconst [int32(int8(c))])
669 (MOVBUreg (MOVWconst [c])) => (MOVWconst [int32(uint8(c))])
670 (MOVHreg (MOVWconst [c])) => (MOVWconst [int32(int16(c))])
671 (MOVHUreg (MOVWconst [c])) => (MOVWconst [int32(uint16(c))])
672 (MOVWreg (MOVWconst [c])) => (MOVWconst [c])
673
674 // constant comparisons
675 (SGTconst [c] (MOVWconst [d])) && c > d => (MOVWconst [1])
676 (SGTconst [c] (MOVWconst [d])) && c <= d => (MOVWconst [0])
677 (SGTUconst [c] (MOVWconst [d])) && uint32(c) > uint32(d) => (MOVWconst [1])
678 (SGTUconst [c] (MOVWconst [d])) && uint32(c) <= uint32(d) => (MOVWconst [0])
679 (SGTzero (MOVWconst [d])) && d > 0 => (MOVWconst [1])
680 (SGTzero (MOVWconst [d])) && d <= 0 => (MOVWconst [0])
681 (SGTUzero (MOVWconst [d])) && d != 0 => (MOVWconst [1])
682 (SGTUzero (MOVWconst [d])) && d == 0 => (MOVWconst [0])
683
684 // other known comparisons
685 (SGTconst [c] (MOVBreg _)) && 0x7f < c => (MOVWconst [1])
686 (SGTconst [c] (MOVBreg _)) && c <= -0x80 => (MOVWconst [0])
687 (SGTconst [c] (MOVBUreg _)) && 0xff < c => (MOVWconst [1])
688 (SGTconst [c] (MOVBUreg _)) && c < 0 => (MOVWconst [0])
689 (SGTUconst [c] (MOVBUreg _)) && 0xff < uint32(c) => (MOVWconst [1])
690 (SGTconst [c] (MOVHreg _)) && 0x7fff < c => (MOVWconst [1])
691 (SGTconst [c] (MOVHreg _)) && c <= -0x8000 => (MOVWconst [0])
692 (SGTconst [c] (MOVHUreg _)) && 0xffff < c => (MOVWconst [1])
693 (SGTconst [c] (MOVHUreg _)) && c < 0 => (MOVWconst [0])
694 (SGTUconst [c] (MOVHUreg _)) && 0xffff < uint32(c) => (MOVWconst [1])
695 (SGTconst [c] (ANDconst [m] _)) && 0 <= m && m < c => (MOVWconst [1])
696 (SGTUconst [c] (ANDconst [m] _)) && uint32(m) < uint32(c) => (MOVWconst [1])
697 (SGTconst [c] (SRLconst _ [d])) && 0 <= c && uint32(d) <= 31 && 0xffffffff>>uint32(d) < uint32(c) => (MOVWconst [1])
698 (SGTUconst [c] (SRLconst _ [d])) && uint32(d) <= 31 && 0xffffffff>>uint32(d) < uint32(c) => (MOVWconst [1])
699
700 // absorb constants into branches
701 (EQ (MOVWconst [0]) yes no) => (First yes no)
702 (EQ (MOVWconst [c]) yes no) && c != 0 => (First no yes)
703 (NE (MOVWconst [0]) yes no) => (First no yes)
704 (NE (MOVWconst [c]) yes no) && c != 0 => (First yes no)
705 (LTZ (MOVWconst [c]) yes no) && c < 0 => (First yes no)
706 (LTZ (MOVWconst [c]) yes no) && c >= 0 => (First no yes)
707 (LEZ (MOVWconst [c]) yes no) && c <= 0 => (First yes no)
708 (LEZ (MOVWconst [c]) yes no) && c > 0 => (First no yes)
709 (GTZ (MOVWconst [c]) yes no) && c > 0 => (First yes no)
710 (GTZ (MOVWconst [c]) yes no) && c <= 0 => (First no yes)
711 (GEZ (MOVWconst [c]) yes no) && c >= 0 => (First yes no)
712 (GEZ (MOVWconst [c]) yes no) && c < 0 => (First no yes)
713
714 // conditional move
715 (CMOVZ _ f (MOVWconst [0])) => f
716 (CMOVZ a _ (MOVWconst [c])) && c!=0 => a
717 (CMOVZzero _ (MOVWconst [0])) => (MOVWconst [0])
718 (CMOVZzero a (MOVWconst [c])) && c!=0 => a
719 (CMOVZ a (MOVWconst [0]) c) => (CMOVZzero a c)
720
721 // atomic
722 (LoweredAtomicStore32 ptr (MOVWconst [0]) mem) => (LoweredAtomicStorezero ptr mem)
723 (LoweredAtomicAdd ptr (MOVWconst [c]) mem) && is16Bit(int64(c)) => (LoweredAtomicAddconst [c] ptr mem)
724
725
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