1 // Copyright 2016 The Go Authors. All rights reserved.
2 // Use of this source code is governed by a BSD-style
3 // license that can be found in the LICENSE file.
4
5 (Add(Ptr|32|16|8) ...) => (ADD ...)
6 (Add(32|64)F ...) => (ADD(F|D) ...)
7
8 (Select0 (Add32carry <t> x y)) => (ADD <t.FieldType(0)> x y)
9 (Select1 (Add32carry <t> x y)) => (SGTU <typ.Bool> x (ADD <t.FieldType(0)> x y))
10 (Add32withcarry <t> x y c) => (ADD c (ADD <t> x y))
11
12 (Select0 (Add32carrywithcarry <t> x y c)) => (ADD <t.FieldType(0)> c (ADD <t.FieldType(0)> x y))
13 (Select1 (Add32carrywithcarry <t> x y c)) =>
14 (OR <typ.Bool>
15 (SGTU <typ.Bool> x xy:(ADD <t.FieldType(0)> x y))
16 (SGTU <typ.Bool> xy (ADD <t.FieldType(0)> c xy)))
17
18 (Sub(Ptr|32|16|8) ...) => (SUB ...)
19 (Sub(32|64)F ...) => (SUB(F|D) ...)
20
21 (Select0 (Sub32carry <t> x y)) => (SUB <t.FieldType(0)> x y)
22 (Select1 (Sub32carry <t> x y)) => (SGTU <typ.Bool> (SUB <t.FieldType(0)> x y) x)
23 (Sub32withcarry <t> x y c) => (SUB (SUB <t> x y) c)
24
25 (Mul(32|16|8) ...) => (MUL ...)
26 (Mul(32|64)F ...) => (MUL(F|D) ...)
27
28 (Hmul(32|32u) x y) => (Select0 (MUL(T|TU) x y))
29 (Mul32uhilo ...) => (MULTU ...)
30
31 (Div32 x y) => (Select1 (DIV x y))
32 (Div32u x y) => (Select1 (DIVU x y))
33 (Div16 x y) => (Select1 (DIV (SignExt16to32 x) (SignExt16to32 y)))
34 (Div16u x y) => (Select1 (DIVU (ZeroExt16to32 x) (ZeroExt16to32 y)))
35 (Div8 x y) => (Select1 (DIV (SignExt8to32 x) (SignExt8to32 y)))
36 (Div8u x y) => (Select1 (DIVU (ZeroExt8to32 x) (ZeroExt8to32 y)))
37 (Div(32|64)F ...) => (DIV(F|D) ...)
38
39 (Mod32 x y) => (Select0 (DIV x y))
40 (Mod32u x y) => (Select0 (DIVU x y))
41 (Mod16 x y) => (Select0 (DIV (SignExt16to32 x) (SignExt16to32 y)))
42 (Mod16u x y) => (Select0 (DIVU (ZeroExt16to32 x) (ZeroExt16to32 y)))
43 (Mod8 x y) => (Select0 (DIV (SignExt8to32 x) (SignExt8to32 y)))
44 (Mod8u x y) => (Select0 (DIVU (ZeroExt8to32 x) (ZeroExt8to32 y)))
45
46 // math package intrinsics
47 (Abs ...) => (ABSD ...)
48
49 // (x + y) / 2 with x>=y becomes (x - y) / 2 + y
50 (Avg32u <t> x y) => (ADD (SRLconst <t> (SUB <t> x y) [1]) y)
51
52 (And(32|16|8) ...) => (AND ...)
53 (Or(32|16|8) ...) => (OR ...)
54 (Xor(32|16|8) ...) => (XOR ...)
55
56 // constant shifts
57 // generic opt rewrites all constant shifts to shift by Const64
58 (Lsh32x64 x (Const64 [c])) && uint32(c) < 32 => (SLLconst x [int32(c)])
59 (Rsh32x64 x (Const64 [c])) && uint32(c) < 32 => (SRAconst x [int32(c)])
60 (Rsh32Ux64 x (Const64 [c])) && uint32(c) < 32 => (SRLconst x [int32(c)])
61 (Lsh16x64 x (Const64 [c])) && uint32(c) < 16 => (SLLconst x [int32(c)])
62 (Rsh16x64 x (Const64 [c])) && uint32(c) < 16 => (SRAconst (SLLconst <typ.UInt32> x [16]) [int32(c+16)])
63 (Rsh16Ux64 x (Const64 [c])) && uint32(c) < 16 => (SRLconst (SLLconst <typ.UInt32> x [16]) [int32(c+16)])
64 (Lsh8x64 x (Const64 [c])) && uint32(c) < 8 => (SLLconst x [int32(c)])
65 (Rsh8x64 x (Const64 [c])) && uint32(c) < 8 => (SRAconst (SLLconst <typ.UInt32> x [24]) [int32(c+24)])
66 (Rsh8Ux64 x (Const64 [c])) && uint32(c) < 8 => (SRLconst (SLLconst <typ.UInt32> x [24]) [int32(c+24)])
67
68 // large constant shifts
69 (Lsh32x64 _ (Const64 [c])) && uint32(c) >= 32 => (MOVWconst [0])
70 (Rsh32Ux64 _ (Const64 [c])) && uint32(c) >= 32 => (MOVWconst [0])
71 (Lsh16x64 _ (Const64 [c])) && uint32(c) >= 16 => (MOVWconst [0])
72 (Rsh16Ux64 _ (Const64 [c])) && uint32(c) >= 16 => (MOVWconst [0])
73 (Lsh8x64 _ (Const64 [c])) && uint32(c) >= 8 => (MOVWconst [0])
74 (Rsh8Ux64 _ (Const64 [c])) && uint32(c) >= 8 => (MOVWconst [0])
75
76 // large constant signed right shift, we leave the sign bit
77 (Rsh32x64 x (Const64 [c])) && uint32(c) >= 32 => (SRAconst x [31])
78 (Rsh16x64 x (Const64 [c])) && uint32(c) >= 16 => (SRAconst (SLLconst <typ.UInt32> x [16]) [31])
79 (Rsh8x64 x (Const64 [c])) && uint32(c) >= 8 => (SRAconst (SLLconst <typ.UInt32> x [24]) [31])
80
81 // shifts
82 // hardware instruction uses only the low 5 bits of the shift
83 // we compare to 32 to ensure Go semantics for large shifts
84 (Lsh32x32 <t> x y) => (CMOVZ (SLL <t> x y) (MOVWconst [0]) (SGTUconst [32] y))
85 (Lsh32x16 <t> x y) => (CMOVZ (SLL <t> x (ZeroExt16to32 y) ) (MOVWconst [0]) (SGTUconst [32] (ZeroExt16to32 y)))
86 (Lsh32x8 <t> x y) => (CMOVZ (SLL <t> x (ZeroExt8to32 y) ) (MOVWconst [0]) (SGTUconst [32] (ZeroExt8to32 y)))
87
88 (Lsh16x32 <t> x y) => (CMOVZ (SLL <t> x y) (MOVWconst [0]) (SGTUconst [32] y))
89 (Lsh16x16 <t> x y) => (CMOVZ (SLL <t> x (ZeroExt16to32 y) ) (MOVWconst [0]) (SGTUconst [32] (ZeroExt16to32 y)))
90 (Lsh16x8 <t> x y) => (CMOVZ (SLL <t> x (ZeroExt8to32 y) ) (MOVWconst [0]) (SGTUconst [32] (ZeroExt8to32 y)))
91
92 (Lsh8x32 <t> x y) => (CMOVZ (SLL <t> x y) (MOVWconst [0]) (SGTUconst [32] y))
93 (Lsh8x16 <t> x y) => (CMOVZ (SLL <t> x (ZeroExt16to32 y) ) (MOVWconst [0]) (SGTUconst [32] (ZeroExt16to32 y)))
94 (Lsh8x8 <t> x y) => (CMOVZ (SLL <t> x (ZeroExt8to32 y) ) (MOVWconst [0]) (SGTUconst [32] (ZeroExt8to32 y)))
95
96 (Rsh32Ux32 <t> x y) => (CMOVZ (SRL <t> x y) (MOVWconst [0]) (SGTUconst [32] y))
97 (Rsh32Ux16 <t> x y) => (CMOVZ (SRL <t> x (ZeroExt16to32 y) ) (MOVWconst [0]) (SGTUconst [32] (ZeroExt16to32 y)))
98 (Rsh32Ux8 <t> x y) => (CMOVZ (SRL <t> x (ZeroExt8to32 y) ) (MOVWconst [0]) (SGTUconst [32] (ZeroExt8to32 y)))
99
100 (Rsh16Ux32 <t> x y) => (CMOVZ (SRL <t> (ZeroExt16to32 x) y) (MOVWconst [0]) (SGTUconst [32] y))
101 (Rsh16Ux16 <t> x y) => (CMOVZ (SRL <t> (ZeroExt16to32 x) (ZeroExt16to32 y) ) (MOVWconst [0]) (SGTUconst [32] (ZeroExt16to32 y)))
102 (Rsh16Ux8 <t> x y) => (CMOVZ (SRL <t> (ZeroExt16to32 x) (ZeroExt8to32 y) ) (MOVWconst [0]) (SGTUconst [32] (ZeroExt8to32 y)))
103
104 (Rsh8Ux32 <t> x y) => (CMOVZ (SRL <t> (ZeroExt8to32 x) y) (MOVWconst [0]) (SGTUconst [32] y))
105 (Rsh8Ux16 <t> x y) => (CMOVZ (SRL <t> (ZeroExt8to32 x) (ZeroExt16to32 y) ) (MOVWconst [0]) (SGTUconst [32] (ZeroExt16to32 y)))
106 (Rsh8Ux8 <t> x y) => (CMOVZ (SRL <t> (ZeroExt8to32 x) (ZeroExt8to32 y) ) (MOVWconst [0]) (SGTUconst [32] (ZeroExt8to32 y)))
107
108 (Rsh32x32 x y) => (SRA x ( CMOVZ <typ.UInt32> y (MOVWconst [31]) (SGTUconst [32] y)))
109 (Rsh32x16 x y) => (SRA x ( CMOVZ <typ.UInt32> (ZeroExt16to32 y) (MOVWconst [31]) (SGTUconst [32] (ZeroExt16to32 y))))
110 (Rsh32x8 x y) => (SRA x ( CMOVZ <typ.UInt32> (ZeroExt8to32 y) (MOVWconst [31]) (SGTUconst [32] (ZeroExt8to32 y))))
111
112 (Rsh16x32 x y) => (SRA (SignExt16to32 x) ( CMOVZ <typ.UInt32> y (MOVWconst [31]) (SGTUconst [32] y)))
113 (Rsh16x16 x y) => (SRA (SignExt16to32 x) ( CMOVZ <typ.UInt32> (ZeroExt16to32 y) (MOVWconst [31]) (SGTUconst [32] (ZeroExt16to32 y))))
114 (Rsh16x8 x y) => (SRA (SignExt16to32 x) ( CMOVZ <typ.UInt32> (ZeroExt8to32 y) (MOVWconst [31]) (SGTUconst [32] (ZeroExt8to32 y))))
115
116 (Rsh8x32 x y) => (SRA (SignExt16to32 x) ( CMOVZ <typ.UInt32> y (MOVWconst [31]) (SGTUconst [32] y)))
117 (Rsh8x16 x y) => (SRA (SignExt16to32 x) ( CMOVZ <typ.UInt32> (ZeroExt16to32 y) (MOVWconst [31]) (SGTUconst [32] (ZeroExt16to32 y))))
118 (Rsh8x8 x y) => (SRA (SignExt16to32 x) ( CMOVZ <typ.UInt32> (ZeroExt8to32 y) (MOVWconst [31]) (SGTUconst [32] (ZeroExt8to32 y))))
119
120 // rotates
121 (RotateLeft8 <t> x (MOVWconst [c])) => (Or8 (Lsh8x32 <t> x (MOVWconst [c&7])) (Rsh8Ux32 <t> x (MOVWconst [-c&7])))
122 (RotateLeft16 <t> x (MOVWconst [c])) => (Or16 (Lsh16x32 <t> x (MOVWconst [c&15])) (Rsh16Ux32 <t> x (MOVWconst [-c&15])))
123 (RotateLeft32 <t> x (MOVWconst [c])) => (Or32 (Lsh32x32 <t> x (MOVWconst [c&31])) (Rsh32Ux32 <t> x (MOVWconst [-c&31])))
124 (RotateLeft64 <t> x (MOVWconst [c])) => (Or64 (Lsh64x32 <t> x (MOVWconst [c&63])) (Rsh64Ux32 <t> x (MOVWconst [-c&63])))
125
126 // unary ops
127 (Neg(32|16|8) ...) => (NEG ...)
128 (Neg(32|64)F ...) => (NEG(F|D) ...)
129
130 (Com(32|16|8) x) => (NORconst [0] x)
131
132 (Sqrt ...) => (SQRTD ...)
133 (Sqrt32 ...) => (SQRTF ...)
134
135 (Ctz(32|16|8)NonZero ...) => (Ctz32 ...)
136
137 // count trailing zero
138 // 32 - CLZ(x&-x - 1)
139 (Ctz32 <t> x) => (SUB (MOVWconst [32]) (CLZ <t> (SUBconst <t> [1] (AND <t> x (NEG <t> x)))))
140 (Ctz16 x) => (Ctz32 (Or32 <typ.UInt32> x (MOVWconst [1<<16])))
141 (Ctz8 x) => (Ctz32 (Or32 <typ.UInt32> x (MOVWconst [1<<8])))
142
143 // bit length
144 (BitLen32 <t> x) => (SUB (MOVWconst [32]) (CLZ <t> x))
145 (BitLen(16|8) x) => (BitLen32 (ZeroExt(16|8)to32 x))
146
147 // boolean ops -- booleans are represented with 0=false, 1=true
148 (AndB ...) => (AND ...)
149 (OrB ...) => (OR ...)
150 (EqB x y) => (XORconst [1] (XOR <typ.Bool> x y))
151 (NeqB ...) => (XOR ...)
152 (Not x) => (XORconst [1] x)
153
154 // constants
155 (Const(32|16|8) [val]) => (MOVWconst [int32(val)])
156 (Const(32|64)F ...) => (MOV(F|D)const ...)
157 (ConstNil) => (MOVWconst [0])
158 (ConstBool [t]) => (MOVWconst [b2i32(t)])
159
160 // truncations
161 // Because we ignore high parts of registers, truncates are just copies.
162 (Trunc16to8 ...) => (Copy ...)
163 (Trunc32to8 ...) => (Copy ...)
164 (Trunc32to16 ...) => (Copy ...)
165
166 // Zero-/Sign-extensions
167 (ZeroExt8to16 ...) => (MOVBUreg ...)
168 (ZeroExt8to32 ...) => (MOVBUreg ...)
169 (ZeroExt16to32 ...) => (MOVHUreg ...)
170
171 (SignExt8to16 ...) => (MOVBreg ...)
172 (SignExt8to32 ...) => (MOVBreg ...)
173 (SignExt16to32 ...) => (MOVHreg ...)
174
175 (Signmask x) => (SRAconst x [31])
176 (Zeromask x) => (NEG (SGTU x (MOVWconst [0])))
177 (Slicemask <t> x) => (SRAconst (NEG <t> x) [31])
178
179 // float-int conversion
180 (Cvt32to(32|64)F ...) => (MOVW(F|D) ...)
181 (Cvt(32|64)Fto32 ...) => (TRUNC(F|D)W ...)
182 (Cvt32Fto64F ...) => (MOVFD ...)
183 (Cvt64Fto32F ...) => (MOVDF ...)
184
185 (CvtBoolToUint8 ...) => (Copy ...)
186
187 (Round(32|64)F ...) => (Copy ...)
188
189 // comparisons
190 (Eq8 x y) => (SGTUconst [1] (XOR (ZeroExt8to32 x) (ZeroExt8to32 y)))
191 (Eq16 x y) => (SGTUconst [1] (XOR (ZeroExt16to32 x) (ZeroExt16to32 y)))
192 (Eq32 x y) => (SGTUconst [1] (XOR x y))
193 (EqPtr x y) => (SGTUconst [1] (XOR x y))
194 (Eq(32|64)F x y) => (FPFlagTrue (CMPEQ(F|D) x y))
195
196 (Neq8 x y) => (SGTU (XOR (ZeroExt8to32 x) (ZeroExt8to32 y)) (MOVWconst [0]))
197 (Neq16 x y) => (SGTU (XOR (ZeroExt16to32 x) (ZeroExt16to32 y)) (MOVWconst [0]))
198 (Neq32 x y) => (SGTU (XOR x y) (MOVWconst [0]))
199 (NeqPtr x y) => (SGTU (XOR x y) (MOVWconst [0]))
200 (Neq(32|64)F x y) => (FPFlagFalse (CMPEQ(F|D) x y))
201
202 (Less8 x y) => (SGT (SignExt8to32 y) (SignExt8to32 x))
203 (Less16 x y) => (SGT (SignExt16to32 y) (SignExt16to32 x))
204 (Less32 x y) => (SGT y x)
205 (Less(32|64)F x y) => (FPFlagTrue (CMPGT(F|D) y x)) // reverse operands to work around NaN
206
207 (Less8U x y) => (SGTU (ZeroExt8to32 y) (ZeroExt8to32 x))
208 (Less16U x y) => (SGTU (ZeroExt16to32 y) (ZeroExt16to32 x))
209 (Less32U x y) => (SGTU y x)
210
211 (Leq8 x y) => (XORconst [1] (SGT (SignExt8to32 x) (SignExt8to32 y)))
212 (Leq16 x y) => (XORconst [1] (SGT (SignExt16to32 x) (SignExt16to32 y)))
213 (Leq32 x y) => (XORconst [1] (SGT x y))
214 (Leq(32|64)F x y) => (FPFlagTrue (CMPGE(F|D) y x)) // reverse operands to work around NaN
215
216 (Leq8U x y) => (XORconst [1] (SGTU (ZeroExt8to32 x) (ZeroExt8to32 y)))
217 (Leq16U x y) => (XORconst [1] (SGTU (ZeroExt16to32 x) (ZeroExt16to32 y)))
218 (Leq32U x y) => (XORconst [1] (SGTU x y))
219
220 (OffPtr [off] ptr:(SP)) => (MOVWaddr [int32(off)] ptr)
221 (OffPtr [off] ptr) => (ADDconst [int32(off)] ptr)
222
223 (Addr {sym} base) => (MOVWaddr {sym} base)
224 (LocalAddr <t> {sym} base mem) && t.Elem().HasPointers() => (MOVWaddr {sym} (SPanchored base mem))
225 (LocalAddr <t> {sym} base _) && !t.Elem().HasPointers() => (MOVWaddr {sym} base)
226
227 // loads
228 (Load <t> ptr mem) && t.IsBoolean() => (MOVBUload ptr mem)
229 (Load <t> ptr mem) && (is8BitInt(t) && t.IsSigned()) => (MOVBload ptr mem)
230 (Load <t> ptr mem) && (is8BitInt(t) && !t.IsSigned()) => (MOVBUload ptr mem)
231 (Load <t> ptr mem) && (is16BitInt(t) && t.IsSigned()) => (MOVHload ptr mem)
232 (Load <t> ptr mem) && (is16BitInt(t) && !t.IsSigned()) => (MOVHUload ptr mem)
233 (Load <t> ptr mem) && (is32BitInt(t) || isPtr(t)) => (MOVWload ptr mem)
234 (Load <t> ptr mem) && is32BitFloat(t) => (MOVFload ptr mem)
235 (Load <t> ptr mem) && is64BitFloat(t) => (MOVDload ptr mem)
236
237 // stores
238 (Store {t} ptr val mem) && t.Size() == 1 => (MOVBstore ptr val mem)
239 (Store {t} ptr val mem) && t.Size() == 2 => (MOVHstore ptr val mem)
240 (Store {t} ptr val mem) && t.Size() == 4 && !t.IsFloat() => (MOVWstore ptr val mem)
241 (Store {t} ptr val mem) && t.Size() == 4 && t.IsFloat() => (MOVFstore ptr val mem)
242 (Store {t} ptr val mem) && t.Size() == 8 && t.IsFloat() => (MOVDstore ptr val mem)
243
244 // float <=> int register moves, with no conversion.
245 // These come up when compiling math.{Float32bits, Float32frombits}.
246 (MOVWload [off] {sym} ptr (MOVFstore [off] {sym} ptr val _)) => (MOVWfpgp val)
247 (MOVFload [off] {sym} ptr (MOVWstore [off] {sym} ptr val _)) => (MOVWgpfp val)
248
249 // Similarly for stores, if we see a store after FPR <=> GPR move, then redirect store to use the other register set.
250 (MOVWstore [off] {sym} ptr (MOVWfpgp val) mem) => (MOVFstore [off] {sym} ptr val mem)
251 (MOVFstore [off] {sym} ptr (MOVWgpfp val) mem) => (MOVWstore [off] {sym} ptr val mem)
252
253 // zero instructions
254 (Zero [0] _ mem) => mem
255 (Zero [1] ptr mem) => (MOVBstore ptr (MOVWconst [0]) mem)
256 (Zero [2] {t} ptr mem) && t.Alignment()%2 == 0 =>
257 (MOVHstore ptr (MOVWconst [0]) mem)
258 (Zero [2] ptr mem) =>
259 (MOVBstore [1] ptr (MOVWconst [0])
260 (MOVBstore [0] ptr (MOVWconst [0]) mem))
261 (Zero [4] {t} ptr mem) && t.Alignment()%4 == 0 =>
262 (MOVWstore ptr (MOVWconst [0]) mem)
263 (Zero [4] {t} ptr mem) && t.Alignment()%2 == 0 =>
264 (MOVHstore [2] ptr (MOVWconst [0])
265 (MOVHstore [0] ptr (MOVWconst [0]) mem))
266 (Zero [4] ptr mem) =>
267 (MOVBstore [3] ptr (MOVWconst [0])
268 (MOVBstore [2] ptr (MOVWconst [0])
269 (MOVBstore [1] ptr (MOVWconst [0])
270 (MOVBstore [0] ptr (MOVWconst [0]) mem))))
271 (Zero [3] ptr mem) =>
272 (MOVBstore [2] ptr (MOVWconst [0])
273 (MOVBstore [1] ptr (MOVWconst [0])
274 (MOVBstore [0] ptr (MOVWconst [0]) mem)))
275 (Zero [6] {t} ptr mem) && t.Alignment()%2 == 0 =>
276 (MOVHstore [4] ptr (MOVWconst [0])
277 (MOVHstore [2] ptr (MOVWconst [0])
278 (MOVHstore [0] ptr (MOVWconst [0]) mem)))
279 (Zero [8] {t} ptr mem) && t.Alignment()%4 == 0 =>
280 (MOVWstore [4] ptr (MOVWconst [0])
281 (MOVWstore [0] ptr (MOVWconst [0]) mem))
282 (Zero [12] {t} ptr mem) && t.Alignment()%4 == 0 =>
283 (MOVWstore [8] ptr (MOVWconst [0])
284 (MOVWstore [4] ptr (MOVWconst [0])
285 (MOVWstore [0] ptr (MOVWconst [0]) mem)))
286 (Zero [16] {t} ptr mem) && t.Alignment()%4 == 0 =>
287 (MOVWstore [12] ptr (MOVWconst [0])
288 (MOVWstore [8] ptr (MOVWconst [0])
289 (MOVWstore [4] ptr (MOVWconst [0])
290 (MOVWstore [0] ptr (MOVWconst [0]) mem))))
291
292 // large or unaligned zeroing uses a loop
293 (Zero [s] {t} ptr mem)
294 && (s > 16 || t.Alignment()%4 != 0) =>
295 (LoweredZero [int32(t.Alignment())]
296 ptr
297 (ADDconst <ptr.Type> ptr [int32(s-moveSize(t.Alignment(), config))])
298 mem)
299
300 // moves
301 (Move [0] _ _ mem) => mem
302 (Move [1] dst src mem) => (MOVBstore dst (MOVBUload src mem) mem)
303 (Move [2] {t} dst src mem) && t.Alignment()%2 == 0 =>
304 (MOVHstore dst (MOVHUload src mem) mem)
305 (Move [2] dst src mem) =>
306 (MOVBstore [1] dst (MOVBUload [1] src mem)
307 (MOVBstore dst (MOVBUload src mem) mem))
308 (Move [4] {t} dst src mem) && t.Alignment()%4 == 0 =>
309 (MOVWstore dst (MOVWload src mem) mem)
310 (Move [4] {t} dst src mem) && t.Alignment()%2 == 0 =>
311 (MOVHstore [2] dst (MOVHUload [2] src mem)
312 (MOVHstore dst (MOVHUload src mem) mem))
313 (Move [4] dst src mem) =>
314 (MOVBstore [3] dst (MOVBUload [3] src mem)
315 (MOVBstore [2] dst (MOVBUload [2] src mem)
316 (MOVBstore [1] dst (MOVBUload [1] src mem)
317 (MOVBstore dst (MOVBUload src mem) mem))))
318 (Move [3] dst src mem) =>
319 (MOVBstore [2] dst (MOVBUload [2] src mem)
320 (MOVBstore [1] dst (MOVBUload [1] src mem)
321 (MOVBstore dst (MOVBUload src mem) mem)))
322 (Move [8] {t} dst src mem) && t.Alignment()%4 == 0 =>
323 (MOVWstore [4] dst (MOVWload [4] src mem)
324 (MOVWstore dst (MOVWload src mem) mem))
325 (Move [8] {t} dst src mem) && t.Alignment()%2 == 0 =>
326 (MOVHstore [6] dst (MOVHload [6] src mem)
327 (MOVHstore [4] dst (MOVHload [4] src mem)
328 (MOVHstore [2] dst (MOVHload [2] src mem)
329 (MOVHstore dst (MOVHload src mem) mem))))
330 (Move [6] {t} dst src mem) && t.Alignment()%2 == 0 =>
331 (MOVHstore [4] dst (MOVHload [4] src mem)
332 (MOVHstore [2] dst (MOVHload [2] src mem)
333 (MOVHstore dst (MOVHload src mem) mem)))
334 (Move [12] {t} dst src mem) && t.Alignment()%4 == 0 =>
335 (MOVWstore [8] dst (MOVWload [8] src mem)
336 (MOVWstore [4] dst (MOVWload [4] src mem)
337 (MOVWstore dst (MOVWload src mem) mem)))
338 (Move [16] {t} dst src mem) && t.Alignment()%4 == 0 =>
339 (MOVWstore [12] dst (MOVWload [12] src mem)
340 (MOVWstore [8] dst (MOVWload [8] src mem)
341 (MOVWstore [4] dst (MOVWload [4] src mem)
342 (MOVWstore dst (MOVWload src mem) mem))))
343
344
345 // large or unaligned move uses a loop
346 (Move [s] {t} dst src mem)
347 && (s > 16 && logLargeCopy(v, s) || t.Alignment()%4 != 0) =>
348 (LoweredMove [int32(t.Alignment())]
349 dst
350 src
351 (ADDconst <src.Type> src [int32(s-moveSize(t.Alignment(), config))])
352 mem)
353
354 // calls
355 (StaticCall ...) => (CALLstatic ...)
356 (ClosureCall ...) => (CALLclosure ...)
357 (InterCall ...) => (CALLinter ...)
358 (TailCall ...) => (CALLtail ...)
359
360 // atomic intrinsics
361 (AtomicLoad(8|32) ...) => (LoweredAtomicLoad(8|32) ...)
362 (AtomicLoadPtr ...) => (LoweredAtomicLoad32 ...)
363
364 (AtomicStore(8|32) ...) => (LoweredAtomicStore(8|32) ...)
365 (AtomicStorePtrNoWB ...) => (LoweredAtomicStore32 ...)
366
367 (AtomicExchange32 ...) => (LoweredAtomicExchange ...)
368 (AtomicAdd32 ...) => (LoweredAtomicAdd ...)
369
370 (AtomicCompareAndSwap32 ...) => (LoweredAtomicCas ...)
371
372 // AtomicOr8(ptr,val) => LoweredAtomicOr(ptr&^3,uint32(val) << ((ptr & 3) * 8))
373 (AtomicOr8 ptr val mem) && !config.BigEndian =>
374 (LoweredAtomicOr (AND <typ.UInt32Ptr> (MOVWconst [^3]) ptr)
375 (SLL <typ.UInt32> (ZeroExt8to32 val)
376 (SLLconst <typ.UInt32> [3]
377 (ANDconst <typ.UInt32> [3] ptr))) mem)
378
379 // AtomicAnd8(ptr,val) => LoweredAtomicAnd(ptr&^3,(uint32(val) << ((ptr & 3) * 8)) | ^(uint32(0xFF) << ((ptr & 3) * 8))))
380 (AtomicAnd8 ptr val mem) && !config.BigEndian =>
381 (LoweredAtomicAnd (AND <typ.UInt32Ptr> (MOVWconst [^3]) ptr)
382 (OR <typ.UInt32> (SLL <typ.UInt32> (ZeroExt8to32 val)
383 (SLLconst <typ.UInt32> [3]
384 (ANDconst <typ.UInt32> [3] ptr)))
385 (NORconst [0] <typ.UInt32> (SLL <typ.UInt32>
386 (MOVWconst [0xff]) (SLLconst <typ.UInt32> [3]
387 (ANDconst <typ.UInt32> [3] ptr))))) mem)
388
389 // AtomicOr8(ptr,val) => LoweredAtomicOr(ptr&^3,uint32(val) << (((ptr^3) & 3) * 8))
390 (AtomicOr8 ptr val mem) && config.BigEndian =>
391 (LoweredAtomicOr (AND <typ.UInt32Ptr> (MOVWconst [^3]) ptr)
392 (SLL <typ.UInt32> (ZeroExt8to32 val)
393 (SLLconst <typ.UInt32> [3]
394 (ANDconst <typ.UInt32> [3]
395 (XORconst <typ.UInt32> [3] ptr)))) mem)
396
397 // AtomicAnd8(ptr,val) => LoweredAtomicAnd(ptr&^3,(uint32(val) << (((ptr^3) & 3) * 8)) | ^(uint32(0xFF) << (((ptr^3) & 3) * 8))))
398 (AtomicAnd8 ptr val mem) && config.BigEndian =>
399 (LoweredAtomicAnd (AND <typ.UInt32Ptr> (MOVWconst [^3]) ptr)
400 (OR <typ.UInt32> (SLL <typ.UInt32> (ZeroExt8to32 val)
401 (SLLconst <typ.UInt32> [3]
402 (ANDconst <typ.UInt32> [3]
403 (XORconst <typ.UInt32> [3] ptr))))
404 (NORconst [0] <typ.UInt32> (SLL <typ.UInt32>
405 (MOVWconst [0xff]) (SLLconst <typ.UInt32> [3]
406 (ANDconst <typ.UInt32> [3]
407 (XORconst <typ.UInt32> [3] ptr)))))) mem)
408
409 (AtomicAnd32 ...) => (LoweredAtomicAnd ...)
410 (AtomicOr32 ...) => (LoweredAtomicOr ...)
411
412
413 // checks
414 (NilCheck ...) => (LoweredNilCheck ...)
415 (IsNonNil ptr) => (SGTU ptr (MOVWconst [0]))
416 (IsInBounds idx len) => (SGTU len idx)
417 (IsSliceInBounds idx len) => (XORconst [1] (SGTU idx len))
418
419 // pseudo-ops
420 (GetClosurePtr ...) => (LoweredGetClosurePtr ...)
421 (GetCallerSP ...) => (LoweredGetCallerSP ...)
422 (GetCallerPC ...) => (LoweredGetCallerPC ...)
423
424 (If cond yes no) => (NE cond yes no)
425
426 // Write barrier.
427 (WB ...) => (LoweredWB ...)
428
429 // Publication barrier as intrinsic
430 (PubBarrier ...) => (LoweredPubBarrier ...)
431
432
433 (PanicBounds ...) => (LoweredPanicBoundsRR ...)
434 (PanicExtend ...) => (LoweredPanicExtendRR ...)
435
436 (LoweredPanicBoundsRR [kind] x (MOVWconst [c]) mem) => (LoweredPanicBoundsRC [kind] x {PanicBoundsC{C:int64(c)}} mem)
437 (LoweredPanicBoundsRR [kind] (MOVWconst [c]) y mem) => (LoweredPanicBoundsCR [kind] {PanicBoundsC{C:int64(c)}} y mem)
438 (LoweredPanicBoundsRC [kind] {p} (MOVWconst [c]) mem) => (LoweredPanicBoundsCC [kind] {PanicBoundsCC{Cx:int64(c), Cy:p.C}} mem)
439
440 (LoweredPanicExtendRR [kind] hi lo (MOVWconst [c]) mem) => (LoweredPanicExtendRC [kind] hi lo {PanicBoundsC{C:int64(c)}} mem)
441 (LoweredPanicExtendRR [kind] (MOVWconst [hi]) (MOVWconst [lo]) y mem) => (LoweredPanicBoundsCR [kind] {PanicBoundsC{C:int64(hi)<<32 + int64(uint32(lo))}} y mem)
442 (LoweredPanicExtendRC [kind] {p} (MOVWconst [hi]) (MOVWconst [lo]) mem) => (LoweredPanicBoundsCC [kind] {PanicBoundsCC{Cx:int64(hi)<<32+int64(uint32(lo)), Cy:p.C}} mem)
443
444 // Optimizations
445
446 // Absorb boolean tests into block
447 (NE (FPFlagTrue cmp) yes no) => (FPT cmp yes no)
448 (NE (FPFlagFalse cmp) yes no) => (FPF cmp yes no)
449 (EQ (FPFlagTrue cmp) yes no) => (FPF cmp yes no)
450 (EQ (FPFlagFalse cmp) yes no) => (FPT cmp yes no)
451 (NE (XORconst [1] cmp:(SGT _ _)) yes no) => (EQ cmp yes no)
452 (NE (XORconst [1] cmp:(SGTU _ _)) yes no) => (EQ cmp yes no)
453 (NE (XORconst [1] cmp:(SGTconst _)) yes no) => (EQ cmp yes no)
454 (NE (XORconst [1] cmp:(SGTUconst _)) yes no) => (EQ cmp yes no)
455 (NE (XORconst [1] cmp:(SGTzero _)) yes no) => (EQ cmp yes no)
456 (NE (XORconst [1] cmp:(SGTUzero _)) yes no) => (EQ cmp yes no)
457 (EQ (XORconst [1] cmp:(SGT _ _)) yes no) => (NE cmp yes no)
458 (EQ (XORconst [1] cmp:(SGTU _ _)) yes no) => (NE cmp yes no)
459 (EQ (XORconst [1] cmp:(SGTconst _)) yes no) => (NE cmp yes no)
460 (EQ (XORconst [1] cmp:(SGTUconst _)) yes no) => (NE cmp yes no)
461 (EQ (XORconst [1] cmp:(SGTzero _)) yes no) => (NE cmp yes no)
462 (EQ (XORconst [1] cmp:(SGTUzero _)) yes no) => (NE cmp yes no)
463 (NE (SGTUconst [1] x) yes no) => (EQ x yes no)
464 (EQ (SGTUconst [1] x) yes no) => (NE x yes no)
465 (NE (SGTUzero x) yes no) => (NE x yes no)
466 (EQ (SGTUzero x) yes no) => (EQ x yes no)
467 (NE (SGTconst [0] x) yes no) => (LTZ x yes no)
468 (EQ (SGTconst [0] x) yes no) => (GEZ x yes no)
469 (NE (SGTzero x) yes no) => (GTZ x yes no)
470 (EQ (SGTzero x) yes no) => (LEZ x yes no)
471
472 // fold offset into address
473 (ADDconst [off1] (MOVWaddr [off2] {sym} ptr)) => (MOVWaddr [off1+off2] {sym} ptr)
474
475 // fold address into load/store
476 (MOVBload [off1] {sym} x:(ADDconst [off2] ptr) mem) && (is16Bit(int64(off1+off2)) || x.Uses == 1) => (MOVBload [off1+off2] {sym} ptr mem)
477 (MOVBUload [off1] {sym} x:(ADDconst [off2] ptr) mem) && (is16Bit(int64(off1+off2)) || x.Uses == 1) => (MOVBUload [off1+off2] {sym} ptr mem)
478 (MOVHload [off1] {sym} x:(ADDconst [off2] ptr) mem) && (is16Bit(int64(off1+off2)) || x.Uses == 1) => (MOVHload [off1+off2] {sym} ptr mem)
479 (MOVHUload [off1] {sym} x:(ADDconst [off2] ptr) mem) && (is16Bit(int64(off1+off2)) || x.Uses == 1) => (MOVHUload [off1+off2] {sym} ptr mem)
480 (MOVWload [off1] {sym} x:(ADDconst [off2] ptr) mem) && (is16Bit(int64(off1+off2)) || x.Uses == 1) => (MOVWload [off1+off2] {sym} ptr mem)
481 (MOVFload [off1] {sym} x:(ADDconst [off2] ptr) mem) && (is16Bit(int64(off1+off2)) || x.Uses == 1) => (MOVFload [off1+off2] {sym} ptr mem)
482 (MOVDload [off1] {sym} x:(ADDconst [off2] ptr) mem) && (is16Bit(int64(off1+off2)) || x.Uses == 1) => (MOVDload [off1+off2] {sym} ptr mem)
483
484 (MOVBstore [off1] {sym} x:(ADDconst [off2] ptr) val mem) && (is16Bit(int64(off1+off2)) || x.Uses == 1) => (MOVBstore [off1+off2] {sym} ptr val mem)
485 (MOVHstore [off1] {sym} x:(ADDconst [off2] ptr) val mem) && (is16Bit(int64(off1+off2)) || x.Uses == 1) => (MOVHstore [off1+off2] {sym} ptr val mem)
486 (MOVWstore [off1] {sym} x:(ADDconst [off2] ptr) val mem) && (is16Bit(int64(off1+off2)) || x.Uses == 1) => (MOVWstore [off1+off2] {sym} ptr val mem)
487 (MOVFstore [off1] {sym} x:(ADDconst [off2] ptr) val mem) && (is16Bit(int64(off1+off2)) || x.Uses == 1) => (MOVFstore [off1+off2] {sym} ptr val mem)
488 (MOVDstore [off1] {sym} x:(ADDconst [off2] ptr) val mem) && (is16Bit(int64(off1+off2)) || x.Uses == 1) => (MOVDstore [off1+off2] {sym} ptr val mem)
489
490 (MOVBstorezero [off1] {sym} x:(ADDconst [off2] ptr) mem) && (is16Bit(int64(off1+off2)) || x.Uses == 1) => (MOVBstorezero [off1+off2] {sym} ptr mem)
491 (MOVHstorezero [off1] {sym} x:(ADDconst [off2] ptr) mem) && (is16Bit(int64(off1+off2)) || x.Uses == 1) => (MOVHstorezero [off1+off2] {sym} ptr mem)
492 (MOVWstorezero [off1] {sym} x:(ADDconst [off2] ptr) mem) && (is16Bit(int64(off1+off2)) || x.Uses == 1) => (MOVWstorezero [off1+off2] {sym} ptr mem)
493
494 (MOVBload [off1] {sym1} (MOVWaddr [off2] {sym2} ptr) mem) && canMergeSym(sym1,sym2) =>
495 (MOVBload [off1+off2] {mergeSym(sym1,sym2)} ptr mem)
496 (MOVBUload [off1] {sym1} (MOVWaddr [off2] {sym2} ptr) mem) && canMergeSym(sym1,sym2) =>
497 (MOVBUload [off1+off2] {mergeSym(sym1,sym2)} ptr mem)
498 (MOVHload [off1] {sym1} (MOVWaddr [off2] {sym2} ptr) mem) && canMergeSym(sym1,sym2) =>
499 (MOVHload [off1+off2] {mergeSym(sym1,sym2)} ptr mem)
500 (MOVHUload [off1] {sym1} (MOVWaddr [off2] {sym2} ptr) mem) && canMergeSym(sym1,sym2) =>
501 (MOVHUload [off1+off2] {mergeSym(sym1,sym2)} ptr mem)
502 (MOVWload [off1] {sym1} (MOVWaddr [off2] {sym2} ptr) mem) && canMergeSym(sym1,sym2) =>
503 (MOVWload [off1+off2] {mergeSym(sym1,sym2)} ptr mem)
504 (MOVFload [off1] {sym1} (MOVWaddr [off2] {sym2} ptr) mem) && canMergeSym(sym1,sym2) =>
505 (MOVFload [off1+off2] {mergeSym(sym1,sym2)} ptr mem)
506 (MOVDload [off1] {sym1} (MOVWaddr [off2] {sym2} ptr) mem) && canMergeSym(sym1,sym2) =>
507 (MOVDload [off1+off2] {mergeSym(sym1,sym2)} ptr mem)
508
509 (MOVBstore [off1] {sym1} (MOVWaddr [off2] {sym2} ptr) val mem) && canMergeSym(sym1,sym2) =>
510 (MOVBstore [off1+off2] {mergeSym(sym1,sym2)} ptr val mem)
511 (MOVHstore [off1] {sym1} (MOVWaddr [off2] {sym2} ptr) val mem) && canMergeSym(sym1,sym2) =>
512 (MOVHstore [off1+off2] {mergeSym(sym1,sym2)} ptr val mem)
513 (MOVWstore [off1] {sym1} (MOVWaddr [off2] {sym2} ptr) val mem) && canMergeSym(sym1,sym2) =>
514 (MOVWstore [off1+off2] {mergeSym(sym1,sym2)} ptr val mem)
515 (MOVFstore [off1] {sym1} (MOVWaddr [off2] {sym2} ptr) val mem) && canMergeSym(sym1,sym2) =>
516 (MOVFstore [off1+off2] {mergeSym(sym1,sym2)} ptr val mem)
517 (MOVDstore [off1] {sym1} (MOVWaddr [off2] {sym2} ptr) val mem) && canMergeSym(sym1,sym2) =>
518 (MOVDstore [off1+off2] {mergeSym(sym1,sym2)} ptr val mem)
519 (MOVBstorezero [off1] {sym1} (MOVWaddr [off2] {sym2} ptr) mem) && canMergeSym(sym1,sym2) =>
520 (MOVBstorezero [off1+off2] {mergeSym(sym1,sym2)} ptr mem)
521 (MOVHstorezero [off1] {sym1} (MOVWaddr [off2] {sym2} ptr) mem) && canMergeSym(sym1,sym2) =>
522 (MOVHstorezero [off1+off2] {mergeSym(sym1,sym2)} ptr mem)
523 (MOVWstorezero [off1] {sym1} (MOVWaddr [off2] {sym2} ptr) mem) && canMergeSym(sym1,sym2) =>
524 (MOVWstorezero [off1+off2] {mergeSym(sym1,sym2)} ptr mem)
525
526 // replace load from same location as preceding store with zero/sign extension (or copy in case of full width)
527 (MOVBload [off] {sym} ptr (MOVBstore [off2] {sym2} ptr2 x _)) && sym == sym2 && off == off2 && isSamePtr(ptr, ptr2) => (MOVBreg x)
528 (MOVBUload [off] {sym} ptr (MOVBstore [off2] {sym2} ptr2 x _)) && sym == sym2 && off == off2 && isSamePtr(ptr, ptr2) => (MOVBUreg x)
529 (MOVHload [off] {sym} ptr (MOVHstore [off2] {sym2} ptr2 x _)) && sym == sym2 && off == off2 && isSamePtr(ptr, ptr2) => (MOVHreg x)
530 (MOVHUload [off] {sym} ptr (MOVHstore [off2] {sym2} ptr2 x _)) && sym == sym2 && off == off2 && isSamePtr(ptr, ptr2) => (MOVHUreg x)
531 (MOVWload [off] {sym} ptr (MOVWstore [off2] {sym2} ptr2 x _)) && sym == sym2 && off == off2 && isSamePtr(ptr, ptr2) => x
532 (MOVFload [off] {sym} ptr (MOVFstore [off2] {sym2} ptr2 x _)) && sym == sym2 && off == off2 && isSamePtr(ptr, ptr2) => x
533 (MOVDload [off] {sym} ptr (MOVDstore [off2] {sym2} ptr2 x _)) && sym == sym2 && off == off2 && isSamePtr(ptr, ptr2) => x
534
535 // store zero
536 (MOVBstore [off] {sym} ptr (MOVWconst [0]) mem) => (MOVBstorezero [off] {sym} ptr mem)
537 (MOVHstore [off] {sym} ptr (MOVWconst [0]) mem) => (MOVHstorezero [off] {sym} ptr mem)
538 (MOVWstore [off] {sym} ptr (MOVWconst [0]) mem) => (MOVWstorezero [off] {sym} ptr mem)
539
540 // don't extend after proper load
541 (MOVBreg x:(MOVBload _ _)) => (MOVWreg x)
542 (MOVBUreg x:(MOVBUload _ _)) => (MOVWreg x)
543 (MOVHreg x:(MOVBload _ _)) => (MOVWreg x)
544 (MOVHreg x:(MOVBUload _ _)) => (MOVWreg x)
545 (MOVHreg x:(MOVHload _ _)) => (MOVWreg x)
546 (MOVHUreg x:(MOVBUload _ _)) => (MOVWreg x)
547 (MOVHUreg x:(MOVHUload _ _)) => (MOVWreg x)
548
549 // fold double extensions
550 (MOVBreg x:(MOVBreg _)) => (MOVWreg x)
551 (MOVBUreg x:(MOVBUreg _)) => (MOVWreg x)
552 (MOVHreg x:(MOVBreg _)) => (MOVWreg x)
553 (MOVHreg x:(MOVBUreg _)) => (MOVWreg x)
554 (MOVHreg x:(MOVHreg _)) => (MOVWreg x)
555 (MOVHUreg x:(MOVBUreg _)) => (MOVWreg x)
556 (MOVHUreg x:(MOVHUreg _)) => (MOVWreg x)
557
558 // sign extended loads
559 // Note: The combined instruction must end up in the same block
560 // as the original load. If not, we end up making a value with
561 // memory type live in two different blocks, which can lead to
562 // multiple memory values alive simultaneously.
563 // Make sure we don't combine these ops if the load has another use.
564 // This prevents a single load from being split into multiple loads
565 // which then might return different values. See test/atomicload.go.
566 (MOVBreg <t> x:(MOVBUload [off] {sym} ptr mem)) && x.Uses == 1 && clobber(x) => @x.Block (MOVBload <t> [off] {sym} ptr mem)
567 (MOVBUreg <t> x:(MOVBload [off] {sym} ptr mem)) && x.Uses == 1 && clobber(x) => @x.Block (MOVBUload <t> [off] {sym} ptr mem)
568 (MOVHreg <t> x:(MOVHUload [off] {sym} ptr mem)) && x.Uses == 1 && clobber(x) => @x.Block (MOVHload <t> [off] {sym} ptr mem)
569 (MOVHUreg <t> x:(MOVHload [off] {sym} ptr mem)) && x.Uses == 1 && clobber(x) => @x.Block (MOVHUload <t> [off] {sym} ptr mem)
570
571 // fold extensions and ANDs together
572 (MOVBUreg (ANDconst [c] x)) => (ANDconst [c&0xff] x)
573 (MOVHUreg (ANDconst [c] x)) => (ANDconst [c&0xffff] x)
574 (MOVBreg (ANDconst [c] x)) && c & 0x80 == 0 => (ANDconst [c&0x7f] x)
575 (MOVHreg (ANDconst [c] x)) && c & 0x8000 == 0 => (ANDconst [c&0x7fff] x)
576
577 // don't extend before store
578 (MOVBstore [off] {sym} ptr (MOVBreg x) mem) => (MOVBstore [off] {sym} ptr x mem)
579 (MOVBstore [off] {sym} ptr (MOVBUreg x) mem) => (MOVBstore [off] {sym} ptr x mem)
580 (MOVBstore [off] {sym} ptr (MOVHreg x) mem) => (MOVBstore [off] {sym} ptr x mem)
581 (MOVBstore [off] {sym} ptr (MOVHUreg x) mem) => (MOVBstore [off] {sym} ptr x mem)
582 (MOVBstore [off] {sym} ptr (MOVWreg x) mem) => (MOVBstore [off] {sym} ptr x mem)
583 (MOVHstore [off] {sym} ptr (MOVHreg x) mem) => (MOVHstore [off] {sym} ptr x mem)
584 (MOVHstore [off] {sym} ptr (MOVHUreg x) mem) => (MOVHstore [off] {sym} ptr x mem)
585 (MOVHstore [off] {sym} ptr (MOVWreg x) mem) => (MOVHstore [off] {sym} ptr x mem)
586 (MOVWstore [off] {sym} ptr (MOVWreg x) mem) => (MOVWstore [off] {sym} ptr x mem)
587
588 // if a register move has only 1 use, just use the same register without emitting instruction
589 // MOVWnop doesn't emit instruction, only for ensuring the type.
590 (MOVWreg x) && x.Uses == 1 => (MOVWnop x)
591
592 // TODO: we should be able to get rid of MOVWnop all together.
593 // But for now, this is enough to get rid of lots of them.
594 (MOVWnop (MOVWconst [c])) => (MOVWconst [c])
595
596 // fold constant into arithmetic ops
597 (ADD x (MOVWconst <t> [c])) && !t.IsPtr() => (ADDconst [c] x)
598 (SUB x (MOVWconst [c])) => (SUBconst [c] x)
599 (AND x (MOVWconst [c])) => (ANDconst [c] x)
600 (OR x (MOVWconst [c])) => (ORconst [c] x)
601 (XOR x (MOVWconst [c])) => (XORconst [c] x)
602 (NOR x (MOVWconst [c])) => (NORconst [c] x)
603
604 (SLL x (MOVWconst [c])) => (SLLconst x [c&31])
605 (SRL x (MOVWconst [c])) => (SRLconst x [c&31])
606 (SRA x (MOVWconst [c])) => (SRAconst x [c&31])
607
608 (SGT (MOVWconst [c]) x) => (SGTconst [c] x)
609 (SGTU (MOVWconst [c]) x) => (SGTUconst [c] x)
610 (SGT x (MOVWconst [0])) => (SGTzero x)
611 (SGTU x (MOVWconst [0])) => (SGTUzero x)
612
613 // mul with constant
614 (Select1 (MULTU (MOVWconst [0]) _ )) => (MOVWconst [0])
615 (Select0 (MULTU (MOVWconst [0]) _ )) => (MOVWconst [0])
616 (Select1 (MULTU (MOVWconst [1]) x )) => x
617 (Select0 (MULTU (MOVWconst [1]) _ )) => (MOVWconst [0])
618 (Select1 (MULTU (MOVWconst [-1]) x )) => (NEG <x.Type> x)
619 (Select0 (MULTU (MOVWconst [-1]) x )) => (CMOVZ (ADDconst <x.Type> [-1] x) (MOVWconst [0]) x)
620 (Select1 (MULTU (MOVWconst [c]) x )) && isUnsignedPowerOfTwo(uint32(c)) => (SLLconst [int32(log32u(uint32(c)))] x)
621 (Select0 (MULTU (MOVWconst [c]) x )) && isUnsignedPowerOfTwo(uint32(c)) => (SRLconst [int32(32-log32u(uint32(c)))] x)
622
623 (MUL (MOVWconst [0]) _ ) => (MOVWconst [0])
624 (MUL (MOVWconst [1]) x ) => x
625 (MUL (MOVWconst [-1]) x ) => (NEG x)
626 (MUL (MOVWconst [c]) x ) && isUnsignedPowerOfTwo(uint32(c)) => (SLLconst [int32(log32u(uint32(c)))] x)
627
628 // generic simplifications
629 (ADD x (NEG y)) => (SUB x y)
630 (SUB x (NEG y)) => (ADD x y)
631 (SUB x x) => (MOVWconst [0])
632 (SUB (MOVWconst [0]) x) => (NEG x)
633 (AND x x) => x
634 (OR x x) => x
635 (XOR x x) => (MOVWconst [0])
636 (NEG (SUB x y)) => (SUB y x)
637 (NEG (NEG x)) => x
638
639 // miscellaneous patterns generated by dec64
640 (AND (SGTUconst [1] x) (SGTUconst [1] y)) => (SGTUconst [1] (OR <x.Type> x y))
641 (OR (SGTUzero x) (SGTUzero y)) => (SGTUzero (OR <x.Type> x y))
642
643 // remove redundant *const ops
644 (ADDconst [0] x) => x
645 (SUBconst [0] x) => x
646 (ANDconst [0] _) => (MOVWconst [0])
647 (ANDconst [-1] x) => x
648 (ORconst [0] x) => x
649 (ORconst [-1] _) => (MOVWconst [-1])
650 (XORconst [0] x) => x
651 (XORconst [-1] x) => (NORconst [0] x)
652
653 // generic constant folding
654 (ADDconst [c] (MOVWconst [d])) => (MOVWconst [int32(c+d)])
655 (ADDconst [c] (ADDconst [d] x)) => (ADDconst [c+d] x)
656 (ADDconst [c] (SUBconst [d] x)) => (ADDconst [c-d] x)
657 (SUBconst [c] (MOVWconst [d])) => (MOVWconst [d-c])
658 (SUBconst [c] (SUBconst [d] x)) => (ADDconst [-c-d] x)
659 (SUBconst [c] (ADDconst [d] x)) => (ADDconst [-c+d] x)
660 (SLLconst [c] (MOVWconst [d])) => (MOVWconst [d<<uint32(c)])
661 (SRLconst [c] (MOVWconst [d])) => (MOVWconst [int32(uint32(d)>>uint32(c))])
662 (SRAconst [c] (MOVWconst [d])) => (MOVWconst [d>>uint32(c)])
663 (MUL (MOVWconst [c]) (MOVWconst [d])) => (MOVWconst [c*d])
664 (Select1 (MULTU (MOVWconst [c]) (MOVWconst [d]))) => (MOVWconst [int32(uint32(c)*uint32(d))])
665 (Select0 (MULTU (MOVWconst [c]) (MOVWconst [d]))) => (MOVWconst [int32((int64(uint32(c))*int64(uint32(d)))>>32)])
666 (Select1 (DIV (MOVWconst [c]) (MOVWconst [d]))) && d != 0 => (MOVWconst [c/d])
667 (Select1 (DIVU (MOVWconst [c]) (MOVWconst [d]))) && d != 0 => (MOVWconst [int32(uint32(c)/uint32(d))])
668 (Select0 (DIV (MOVWconst [c]) (MOVWconst [d]))) && d != 0 => (MOVWconst [c%d])
669 (Select0 (DIVU (MOVWconst [c]) (MOVWconst [d]))) && d != 0 => (MOVWconst [int32(uint32(c)%uint32(d))])
670 (ANDconst [c] (MOVWconst [d])) => (MOVWconst [c&d])
671 (ANDconst [c] (ANDconst [d] x)) => (ANDconst [c&d] x)
672 (ORconst [c] (MOVWconst [d])) => (MOVWconst [c|d])
673 (ORconst [c] (ORconst [d] x)) => (ORconst [c|d] x)
674 (XORconst [c] (MOVWconst [d])) => (MOVWconst [c^d])
675 (XORconst [c] (XORconst [d] x)) => (XORconst [c^d] x)
676 (NORconst [c] (MOVWconst [d])) => (MOVWconst [^(c|d)])
677 (NEG (MOVWconst [c])) => (MOVWconst [-c])
678 (MOVBreg (MOVWconst [c])) => (MOVWconst [int32(int8(c))])
679 (MOVBUreg (MOVWconst [c])) => (MOVWconst [int32(uint8(c))])
680 (MOVHreg (MOVWconst [c])) => (MOVWconst [int32(int16(c))])
681 (MOVHUreg (MOVWconst [c])) => (MOVWconst [int32(uint16(c))])
682 (MOVWreg (MOVWconst [c])) => (MOVWconst [c])
683
684 // constant comparisons
685 (SGTconst [c] (MOVWconst [d])) && c > d => (MOVWconst [1])
686 (SGTconst [c] (MOVWconst [d])) && c <= d => (MOVWconst [0])
687 (SGTUconst [c] (MOVWconst [d])) && uint32(c) > uint32(d) => (MOVWconst [1])
688 (SGTUconst [c] (MOVWconst [d])) && uint32(c) <= uint32(d) => (MOVWconst [0])
689 (SGTzero (MOVWconst [d])) && d > 0 => (MOVWconst [1])
690 (SGTzero (MOVWconst [d])) && d <= 0 => (MOVWconst [0])
691 (SGTUzero (MOVWconst [d])) && d != 0 => (MOVWconst [1])
692 (SGTUzero (MOVWconst [d])) && d == 0 => (MOVWconst [0])
693
694 // other known comparisons
695 (SGTconst [c] (MOVBreg _)) && 0x7f < c => (MOVWconst [1])
696 (SGTconst [c] (MOVBreg _)) && c <= -0x80 => (MOVWconst [0])
697 (SGTconst [c] (MOVBUreg _)) && 0xff < c => (MOVWconst [1])
698 (SGTconst [c] (MOVBUreg _)) && c < 0 => (MOVWconst [0])
699 (SGTUconst [c] (MOVBUreg _)) && 0xff < uint32(c) => (MOVWconst [1])
700 (SGTconst [c] (MOVHreg _)) && 0x7fff < c => (MOVWconst [1])
701 (SGTconst [c] (MOVHreg _)) && c <= -0x8000 => (MOVWconst [0])
702 (SGTconst [c] (MOVHUreg _)) && 0xffff < c => (MOVWconst [1])
703 (SGTconst [c] (MOVHUreg _)) && c < 0 => (MOVWconst [0])
704 (SGTUconst [c] (MOVHUreg _)) && 0xffff < uint32(c) => (MOVWconst [1])
705 (SGTconst [c] (ANDconst [m] _)) && 0 <= m && m < c => (MOVWconst [1])
706 (SGTUconst [c] (ANDconst [m] _)) && uint32(m) < uint32(c) => (MOVWconst [1])
707 (SGTconst [c] (SRLconst _ [d])) && 0 <= c && uint32(d) <= 31 && 0xffffffff>>uint32(d) < uint32(c) => (MOVWconst [1])
708 (SGTUconst [c] (SRLconst _ [d])) && uint32(d) <= 31 && 0xffffffff>>uint32(d) < uint32(c) => (MOVWconst [1])
709
710 // absorb constants into branches
711 (EQ (MOVWconst [0]) yes no) => (First yes no)
712 (EQ (MOVWconst [c]) yes no) && c != 0 => (First no yes)
713 (NE (MOVWconst [0]) yes no) => (First no yes)
714 (NE (MOVWconst [c]) yes no) && c != 0 => (First yes no)
715 (LTZ (MOVWconst [c]) yes no) && c < 0 => (First yes no)
716 (LTZ (MOVWconst [c]) yes no) && c >= 0 => (First no yes)
717 (LEZ (MOVWconst [c]) yes no) && c <= 0 => (First yes no)
718 (LEZ (MOVWconst [c]) yes no) && c > 0 => (First no yes)
719 (GTZ (MOVWconst [c]) yes no) && c > 0 => (First yes no)
720 (GTZ (MOVWconst [c]) yes no) && c <= 0 => (First no yes)
721 (GEZ (MOVWconst [c]) yes no) && c >= 0 => (First yes no)
722 (GEZ (MOVWconst [c]) yes no) && c < 0 => (First no yes)
723
724 // conditional move
725 (CMOVZ _ f (MOVWconst [0])) => f
726 (CMOVZ a _ (MOVWconst [c])) && c!=0 => a
727 (CMOVZzero _ (MOVWconst [0])) => (MOVWconst [0])
728 (CMOVZzero a (MOVWconst [c])) && c!=0 => a
729 (CMOVZ a (MOVWconst [0]) c) => (CMOVZzero a c)
730
731 // atomic
732 (LoweredAtomicStore32 ptr (MOVWconst [0]) mem) => (LoweredAtomicStorezero ptr mem)
733 (LoweredAtomicAdd ptr (MOVWconst [c]) mem) && is16Bit(int64(c)) => (LoweredAtomicAddconst [c] ptr mem)
734
735
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