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4
5 package main
6
7 import "strings"
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30
31 var regNamesLOONG64 = []string{
32 "R0",
33 "R1",
34 "SP",
35 "R4",
36 "R5",
37 "R6",
38 "R7",
39 "R8",
40 "R9",
41 "R10",
42 "R11",
43 "R12",
44 "R13",
45 "R14",
46 "R15",
47 "R16",
48 "R17",
49 "R18",
50 "R19",
51 "R20",
52 "R21",
53 "g",
54 "R23",
55 "R24",
56 "R25",
57 "R26",
58 "R27",
59 "R28",
60 "R29",
61
62 "R31",
63
64 "F0",
65 "F1",
66 "F2",
67 "F3",
68 "F4",
69 "F5",
70 "F6",
71 "F7",
72 "F8",
73 "F9",
74 "F10",
75 "F11",
76 "F12",
77 "F13",
78 "F14",
79 "F15",
80 "F16",
81 "F17",
82 "F18",
83 "F19",
84 "F20",
85 "F21",
86 "F22",
87 "F23",
88 "F24",
89 "F25",
90 "F26",
91 "F27",
92 "F28",
93 "F29",
94 "F30",
95 "F31",
96
97
98
99
100 "SB",
101 }
102
103 func init() {
104
105 if len(regNamesLOONG64) > 64 {
106 panic("too many registers")
107 }
108 num := map[string]int{}
109 for i, name := range regNamesLOONG64 {
110 num[name] = i
111 }
112 buildReg := func(s string) regMask {
113 m := regMask(0)
114 for _, r := range strings.Split(s, " ") {
115 if n, ok := num[r]; ok {
116 m |= regMask(1) << uint(n)
117 continue
118 }
119 panic("register " + r + " not found")
120 }
121 return m
122 }
123
124
125 var (
126 gp = buildReg("R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31")
127 gpg = gp | buildReg("g")
128 gpsp = gp | buildReg("SP")
129 gpspg = gpg | buildReg("SP")
130 gpspsbg = gpspg | buildReg("SB")
131 fp = buildReg("F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31")
132 callerSave = gp | fp | buildReg("g")
133 r1 = buildReg("R20")
134 r2 = buildReg("R21")
135 r3 = buildReg("R23")
136 r4 = buildReg("R24")
137 )
138
139 var (
140 gp01 = regInfo{inputs: nil, outputs: []regMask{gp}}
141 gp11 = regInfo{inputs: []regMask{gpg}, outputs: []regMask{gp}}
142 gp11sp = regInfo{inputs: []regMask{gpspg}, outputs: []regMask{gp}}
143 gp21 = regInfo{inputs: []regMask{gpg, gpg}, outputs: []regMask{gp}}
144 gpload = regInfo{inputs: []regMask{gpspsbg}, outputs: []regMask{gp}}
145 gp2load = regInfo{inputs: []regMask{gpspsbg, gpg}, outputs: []regMask{gp}}
146 gpstore = regInfo{inputs: []regMask{gpspsbg, gpg}}
147 gpstore0 = regInfo{inputs: []regMask{gpspsbg}}
148 gpstore2 = regInfo{inputs: []regMask{gpspsbg, gpg, gpg}}
149 gpxchg = regInfo{inputs: []regMask{gpspsbg, gpg}, outputs: []regMask{gp}}
150 gpcas = regInfo{inputs: []regMask{gpspsbg, gpg, gpg}, outputs: []regMask{gp}}
151 preldreg = regInfo{inputs: []regMask{gpspg}}
152 fp01 = regInfo{inputs: nil, outputs: []regMask{fp}}
153 fp11 = regInfo{inputs: []regMask{fp}, outputs: []regMask{fp}}
154 fp21 = regInfo{inputs: []regMask{fp, fp}, outputs: []regMask{fp}}
155 fp31 = regInfo{inputs: []regMask{fp, fp, fp}, outputs: []regMask{fp}}
156 fp2flags = regInfo{inputs: []regMask{fp, fp}}
157 fpload = regInfo{inputs: []regMask{gpspsbg}, outputs: []regMask{fp}}
158 fp2load = regInfo{inputs: []regMask{gpspsbg, gpg}, outputs: []regMask{fp}}
159 fpstore = regInfo{inputs: []regMask{gpspsbg, fp}}
160 fpstore2 = regInfo{inputs: []regMask{gpspsbg, gpg, fp}}
161 fpgp = regInfo{inputs: []regMask{fp}, outputs: []regMask{gp}}
162 gpfp = regInfo{inputs: []regMask{gp}, outputs: []regMask{fp}}
163 readflags = regInfo{inputs: nil, outputs: []regMask{gp}}
164 )
165 ops := []opData{
166
167 {name: "NEGV", argLength: 1, reg: gp11},
168 {name: "NEGF", argLength: 1, reg: fp11, asm: "NEGF"},
169 {name: "NEGD", argLength: 1, reg: fp11, asm: "NEGD"},
170
171 {name: "SQRTD", argLength: 1, reg: fp11, asm: "SQRTD"},
172 {name: "SQRTF", argLength: 1, reg: fp11, asm: "SQRTF"},
173
174 {name: "ABSD", argLength: 1, reg: fp11, asm: "ABSD"},
175
176 {name: "CLZW", argLength: 1, reg: gp11, asm: "CLZW"},
177 {name: "CLZV", argLength: 1, reg: gp11, asm: "CLZV"},
178 {name: "CTZW", argLength: 1, reg: gp11, asm: "CTZW"},
179 {name: "CTZV", argLength: 1, reg: gp11, asm: "CTZV"},
180
181 {name: "REVB2H", argLength: 1, reg: gp11, asm: "REVB2H"},
182 {name: "REVB2W", argLength: 1, reg: gp11, asm: "REVB2W"},
183 {name: "REVBV", argLength: 1, reg: gp11, asm: "REVBV"},
184
185 {name: "BITREV4B", argLength: 1, reg: gp11, asm: "BITREV4B"},
186 {name: "BITREVW", argLength: 1, reg: gp11, asm: "BITREVW"},
187 {name: "BITREVV", argLength: 1, reg: gp11, asm: "BITREVV"},
188
189 {name: "VPCNT64", argLength: 1, reg: fp11, asm: "VPCNTV"},
190 {name: "VPCNT32", argLength: 1, reg: fp11, asm: "VPCNTW"},
191 {name: "VPCNT16", argLength: 1, reg: fp11, asm: "VPCNTH"},
192
193
194 {name: "ADDV", argLength: 2, reg: gp21, asm: "ADDVU", commutative: true},
195 {name: "ADDVconst", argLength: 1, reg: gp11sp, asm: "ADDVU", aux: "Int64"},
196 {name: "SUBV", argLength: 2, reg: gp21, asm: "SUBVU"},
197 {name: "SUBVconst", argLength: 1, reg: gp11, asm: "SUBVU", aux: "Int64"},
198
199 {name: "MULV", argLength: 2, reg: gp21, asm: "MULV", commutative: true, typ: "Int64"},
200 {name: "MULHV", argLength: 2, reg: gp21, asm: "MULHV", commutative: true, typ: "Int64"},
201 {name: "MULHVU", argLength: 2, reg: gp21, asm: "MULHVU", commutative: true, typ: "UInt64"},
202 {name: "DIVV", argLength: 2, reg: gp21, asm: "DIVV", typ: "Int64"},
203 {name: "DIVVU", argLength: 2, reg: gp21, asm: "DIVVU", typ: "UInt64"},
204 {name: "REMV", argLength: 2, reg: gp21, asm: "REMV", typ: "Int64"},
205 {name: "REMVU", argLength: 2, reg: gp21, asm: "REMVU", typ: "UInt64"},
206
207 {name: "ADDF", argLength: 2, reg: fp21, asm: "ADDF", commutative: true},
208 {name: "ADDD", argLength: 2, reg: fp21, asm: "ADDD", commutative: true},
209 {name: "SUBF", argLength: 2, reg: fp21, asm: "SUBF"},
210 {name: "SUBD", argLength: 2, reg: fp21, asm: "SUBD"},
211 {name: "MULF", argLength: 2, reg: fp21, asm: "MULF", commutative: true},
212 {name: "MULD", argLength: 2, reg: fp21, asm: "MULD", commutative: true},
213 {name: "DIVF", argLength: 2, reg: fp21, asm: "DIVF"},
214 {name: "DIVD", argLength: 2, reg: fp21, asm: "DIVD"},
215
216 {name: "AND", argLength: 2, reg: gp21, asm: "AND", commutative: true},
217 {name: "ANDconst", argLength: 1, reg: gp11, asm: "AND", aux: "Int64"},
218 {name: "OR", argLength: 2, reg: gp21, asm: "OR", commutative: true},
219 {name: "ORconst", argLength: 1, reg: gp11, asm: "OR", aux: "Int64"},
220 {name: "XOR", argLength: 2, reg: gp21, asm: "XOR", commutative: true, typ: "UInt64"},
221 {name: "XORconst", argLength: 1, reg: gp11, asm: "XOR", aux: "Int64", typ: "UInt64"},
222 {name: "NOR", argLength: 2, reg: gp21, asm: "NOR", commutative: true},
223 {name: "NORconst", argLength: 1, reg: gp11, asm: "NOR", aux: "Int64"},
224 {name: "ANDN", argLength: 2, reg: gp21, asm: "ANDN"},
225 {name: "ORN", argLength: 2, reg: gp21, asm: "ORN"},
226
227 {name: "FMADDF", argLength: 3, reg: fp31, asm: "FMADDF", commutative: true, typ: "Float32"},
228 {name: "FMADDD", argLength: 3, reg: fp31, asm: "FMADDD", commutative: true, typ: "Float64"},
229 {name: "FMSUBF", argLength: 3, reg: fp31, asm: "FMSUBF", commutative: true, typ: "Float32"},
230 {name: "FMSUBD", argLength: 3, reg: fp31, asm: "FMSUBD", commutative: true, typ: "Float64"},
231 {name: "FNMADDF", argLength: 3, reg: fp31, asm: "FNMADDF", commutative: true, typ: "Float32"},
232 {name: "FNMADDD", argLength: 3, reg: fp31, asm: "FNMADDD", commutative: true, typ: "Float64"},
233 {name: "FNMSUBF", argLength: 3, reg: fp31, asm: "FNMSUBF", commutative: true, typ: "Float32"},
234 {name: "FNMSUBD", argLength: 3, reg: fp31, asm: "FNMSUBD", commutative: true, typ: "Float64"},
235
236 {name: "FMINF", argLength: 2, reg: fp21, resultNotInArgs: true, asm: "FMINF", commutative: true, typ: "Float32"},
237 {name: "FMIND", argLength: 2, reg: fp21, resultNotInArgs: true, asm: "FMIND", commutative: true, typ: "Float64"},
238 {name: "FMAXF", argLength: 2, reg: fp21, resultNotInArgs: true, asm: "FMAXF", commutative: true, typ: "Float32"},
239 {name: "FMAXD", argLength: 2, reg: fp21, resultNotInArgs: true, asm: "FMAXD", commutative: true, typ: "Float64"},
240
241 {name: "MASKEQZ", argLength: 2, reg: gp21, asm: "MASKEQZ"},
242 {name: "MASKNEZ", argLength: 2, reg: gp21, asm: "MASKNEZ"},
243 {name: "FCOPYSGD", argLength: 2, reg: fp21, asm: "FCOPYSGD"},
244
245
246 {name: "SLL", argLength: 2, reg: gp21, asm: "SLL"},
247 {name: "SLLV", argLength: 2, reg: gp21, asm: "SLLV"},
248 {name: "SLLconst", argLength: 1, reg: gp11, asm: "SLL", aux: "Int64"},
249 {name: "SLLVconst", argLength: 1, reg: gp11, asm: "SLLV", aux: "Int64"},
250 {name: "SRL", argLength: 2, reg: gp21, asm: "SRL"},
251 {name: "SRLV", argLength: 2, reg: gp21, asm: "SRLV"},
252 {name: "SRLconst", argLength: 1, reg: gp11, asm: "SRL", aux: "Int64"},
253 {name: "SRLVconst", argLength: 1, reg: gp11, asm: "SRLV", aux: "Int64"},
254 {name: "SRA", argLength: 2, reg: gp21, asm: "SRA"},
255 {name: "SRAV", argLength: 2, reg: gp21, asm: "SRAV"},
256 {name: "SRAconst", argLength: 1, reg: gp11, asm: "SRA", aux: "Int64"},
257 {name: "SRAVconst", argLength: 1, reg: gp11, asm: "SRAV", aux: "Int64"},
258 {name: "ROTR", argLength: 2, reg: gp21, asm: "ROTR"},
259 {name: "ROTRV", argLength: 2, reg: gp21, asm: "ROTRV"},
260 {name: "ROTRconst", argLength: 1, reg: gp11, asm: "ROTR", aux: "Int64"},
261 {name: "ROTRVconst", argLength: 1, reg: gp11, asm: "ROTRV", aux: "Int64"},
262
263
264 {name: "SGT", argLength: 2, reg: gp21, asm: "SGT", typ: "Bool"},
265 {name: "SGTconst", argLength: 1, reg: gp11, asm: "SGT", aux: "Int64", typ: "Bool"},
266 {name: "SGTU", argLength: 2, reg: gp21, asm: "SGTU", typ: "Bool"},
267 {name: "SGTUconst", argLength: 1, reg: gp11, asm: "SGTU", aux: "Int64", typ: "Bool"},
268
269 {name: "CMPEQF", argLength: 2, reg: fp2flags, asm: "CMPEQF", typ: "Flags"},
270 {name: "CMPEQD", argLength: 2, reg: fp2flags, asm: "CMPEQD", typ: "Flags"},
271 {name: "CMPGEF", argLength: 2, reg: fp2flags, asm: "CMPGEF", typ: "Flags"},
272 {name: "CMPGED", argLength: 2, reg: fp2flags, asm: "CMPGED", typ: "Flags"},
273 {name: "CMPGTF", argLength: 2, reg: fp2flags, asm: "CMPGTF", typ: "Flags"},
274 {name: "CMPGTD", argLength: 2, reg: fp2flags, asm: "CMPGTD", typ: "Flags"},
275
276
277
278
279 {name: "BSTRPICKW", argLength: 1, reg: gp11, asm: "BSTRPICKW", aux: "Int64"},
280 {name: "BSTRPICKV", argLength: 1, reg: gp11, asm: "BSTRPICKV", aux: "Int64"},
281
282
283 {name: "MOVVconst", argLength: 0, reg: gp01, aux: "Int64", asm: "MOVV", typ: "UInt64", rematerializeable: true},
284 {name: "MOVFconst", argLength: 0, reg: fp01, aux: "Float64", asm: "MOVF", typ: "Float32", rematerializeable: true},
285 {name: "MOVDconst", argLength: 0, reg: fp01, aux: "Float64", asm: "MOVD", typ: "Float64", rematerializeable: true},
286
287 {name: "MOVVaddr", argLength: 1, reg: regInfo{inputs: []regMask{buildReg("SP") | buildReg("SB")}, outputs: []regMask{gp}}, aux: "SymOff", asm: "MOVV", rematerializeable: true, symEffect: "Addr"},
288
289 {name: "MOVBload", argLength: 2, reg: gpload, aux: "SymOff", asm: "MOVB", typ: "Int8", faultOnNilArg0: true, symEffect: "Read"},
290 {name: "MOVBUload", argLength: 2, reg: gpload, aux: "SymOff", asm: "MOVBU", typ: "UInt8", faultOnNilArg0: true, symEffect: "Read"},
291 {name: "MOVHload", argLength: 2, reg: gpload, aux: "SymOff", asm: "MOVH", typ: "Int16", faultOnNilArg0: true, symEffect: "Read"},
292 {name: "MOVHUload", argLength: 2, reg: gpload, aux: "SymOff", asm: "MOVHU", typ: "UInt16", faultOnNilArg0: true, symEffect: "Read"},
293 {name: "MOVWload", argLength: 2, reg: gpload, aux: "SymOff", asm: "MOVW", typ: "Int32", faultOnNilArg0: true, symEffect: "Read"},
294 {name: "MOVWUload", argLength: 2, reg: gpload, aux: "SymOff", asm: "MOVWU", typ: "UInt32", faultOnNilArg0: true, symEffect: "Read"},
295 {name: "MOVVload", argLength: 2, reg: gpload, aux: "SymOff", asm: "MOVV", typ: "UInt64", faultOnNilArg0: true, symEffect: "Read"},
296 {name: "MOVFload", argLength: 2, reg: fpload, aux: "SymOff", asm: "MOVF", typ: "Float32", faultOnNilArg0: true, symEffect: "Read"},
297 {name: "MOVDload", argLength: 2, reg: fpload, aux: "SymOff", asm: "MOVD", typ: "Float64", faultOnNilArg0: true, symEffect: "Read"},
298
299
300 {name: "MOVVloadidx", argLength: 3, reg: gp2load, asm: "MOVV", typ: "UInt64"},
301 {name: "MOVWloadidx", argLength: 3, reg: gp2load, asm: "MOVW", typ: "Int32"},
302 {name: "MOVWUloadidx", argLength: 3, reg: gp2load, asm: "MOVWU", typ: "UInt32"},
303 {name: "MOVHloadidx", argLength: 3, reg: gp2load, asm: "MOVH", typ: "Int16"},
304 {name: "MOVHUloadidx", argLength: 3, reg: gp2load, asm: "MOVHU", typ: "UInt16"},
305 {name: "MOVBloadidx", argLength: 3, reg: gp2load, asm: "MOVB", typ: "Int8"},
306 {name: "MOVBUloadidx", argLength: 3, reg: gp2load, asm: "MOVBU", typ: "UInt8"},
307 {name: "MOVFloadidx", argLength: 3, reg: fp2load, asm: "MOVF", typ: "Float32"},
308 {name: "MOVDloadidx", argLength: 3, reg: fp2load, asm: "MOVD", typ: "Float64"},
309
310 {name: "MOVBstore", argLength: 3, reg: gpstore, aux: "SymOff", asm: "MOVB", typ: "Mem", faultOnNilArg0: true, symEffect: "Write"},
311 {name: "MOVHstore", argLength: 3, reg: gpstore, aux: "SymOff", asm: "MOVH", typ: "Mem", faultOnNilArg0: true, symEffect: "Write"},
312 {name: "MOVWstore", argLength: 3, reg: gpstore, aux: "SymOff", asm: "MOVW", typ: "Mem", faultOnNilArg0: true, symEffect: "Write"},
313 {name: "MOVVstore", argLength: 3, reg: gpstore, aux: "SymOff", asm: "MOVV", typ: "Mem", faultOnNilArg0: true, symEffect: "Write"},
314 {name: "MOVFstore", argLength: 3, reg: fpstore, aux: "SymOff", asm: "MOVF", typ: "Mem", faultOnNilArg0: true, symEffect: "Write"},
315 {name: "MOVDstore", argLength: 3, reg: fpstore, aux: "SymOff", asm: "MOVD", typ: "Mem", faultOnNilArg0: true, symEffect: "Write"},
316
317
318 {name: "MOVBstoreidx", argLength: 4, reg: gpstore2, asm: "MOVB", typ: "Mem"},
319 {name: "MOVHstoreidx", argLength: 4, reg: gpstore2, asm: "MOVH", typ: "Mem"},
320 {name: "MOVWstoreidx", argLength: 4, reg: gpstore2, asm: "MOVW", typ: "Mem"},
321 {name: "MOVVstoreidx", argLength: 4, reg: gpstore2, asm: "MOVV", typ: "Mem"},
322 {name: "MOVFstoreidx", argLength: 4, reg: fpstore2, asm: "MOVF", typ: "Mem"},
323 {name: "MOVDstoreidx", argLength: 4, reg: fpstore2, asm: "MOVD", typ: "Mem"},
324
325 {name: "MOVBstorezero", argLength: 2, reg: gpstore0, aux: "SymOff", asm: "MOVB", typ: "Mem", faultOnNilArg0: true, symEffect: "Write"},
326 {name: "MOVHstorezero", argLength: 2, reg: gpstore0, aux: "SymOff", asm: "MOVH", typ: "Mem", faultOnNilArg0: true, symEffect: "Write"},
327 {name: "MOVWstorezero", argLength: 2, reg: gpstore0, aux: "SymOff", asm: "MOVW", typ: "Mem", faultOnNilArg0: true, symEffect: "Write"},
328 {name: "MOVVstorezero", argLength: 2, reg: gpstore0, aux: "SymOff", asm: "MOVV", typ: "Mem", faultOnNilArg0: true, symEffect: "Write"},
329
330
331 {name: "MOVBstorezeroidx", argLength: 3, reg: gpstore, asm: "MOVB", typ: "Mem"},
332 {name: "MOVHstorezeroidx", argLength: 3, reg: gpstore, asm: "MOVH", typ: "Mem"},
333 {name: "MOVWstorezeroidx", argLength: 3, reg: gpstore, asm: "MOVW", typ: "Mem"},
334 {name: "MOVVstorezeroidx", argLength: 3, reg: gpstore, asm: "MOVV", typ: "Mem"},
335
336
337 {name: "MOVWfpgp", argLength: 1, reg: fpgp, asm: "MOVW"},
338 {name: "MOVWgpfp", argLength: 1, reg: gpfp, asm: "MOVW"},
339 {name: "MOVVfpgp", argLength: 1, reg: fpgp, asm: "MOVV"},
340 {name: "MOVVgpfp", argLength: 1, reg: gpfp, asm: "MOVV"},
341
342
343 {name: "MOVBreg", argLength: 1, reg: gp11, asm: "MOVB"},
344 {name: "MOVBUreg", argLength: 1, reg: gp11, asm: "MOVBU"},
345 {name: "MOVHreg", argLength: 1, reg: gp11, asm: "MOVH"},
346 {name: "MOVHUreg", argLength: 1, reg: gp11, asm: "MOVHU"},
347 {name: "MOVWreg", argLength: 1, reg: gp11, asm: "MOVW"},
348 {name: "MOVWUreg", argLength: 1, reg: gp11, asm: "MOVWU"},
349 {name: "MOVVreg", argLength: 1, reg: gp11, asm: "MOVV"},
350
351 {name: "MOVVnop", argLength: 1, reg: regInfo{inputs: []regMask{gp}, outputs: []regMask{gp}}, resultInArg0: true},
352
353 {name: "MOVWF", argLength: 1, reg: fp11, asm: "MOVWF"},
354 {name: "MOVWD", argLength: 1, reg: fp11, asm: "MOVWD"},
355 {name: "MOVVF", argLength: 1, reg: fp11, asm: "MOVVF"},
356 {name: "MOVVD", argLength: 1, reg: fp11, asm: "MOVVD"},
357 {name: "TRUNCFW", argLength: 1, reg: fp11, asm: "TRUNCFW"},
358 {name: "TRUNCDW", argLength: 1, reg: fp11, asm: "TRUNCDW"},
359 {name: "TRUNCFV", argLength: 1, reg: fp11, asm: "TRUNCFV"},
360 {name: "TRUNCDV", argLength: 1, reg: fp11, asm: "TRUNCDV"},
361 {name: "MOVFD", argLength: 1, reg: fp11, asm: "MOVFD"},
362 {name: "MOVDF", argLength: 1, reg: fp11, asm: "MOVDF"},
363
364
365 {name: "LoweredRound32F", argLength: 1, reg: fp11, resultInArg0: true},
366 {name: "LoweredRound64F", argLength: 1, reg: fp11, resultInArg0: true},
367
368
369 {name: "CALLstatic", argLength: -1, reg: regInfo{clobbers: callerSave}, aux: "CallOff", clobberFlags: true, call: true},
370 {name: "CALLtail", argLength: -1, reg: regInfo{clobbers: callerSave}, aux: "CallOff", clobberFlags: true, call: true, tailCall: true},
371 {name: "CALLclosure", argLength: -1, reg: regInfo{inputs: []regMask{gpsp, buildReg("R29"), 0}, clobbers: callerSave}, aux: "CallOff", clobberFlags: true, call: true},
372 {name: "CALLinter", argLength: -1, reg: regInfo{inputs: []regMask{gp}, clobbers: callerSave}, aux: "CallOff", clobberFlags: true, call: true},
373
374
375
376
377
378
379
380 {
381 name: "DUFFZERO",
382 aux: "Int64",
383 argLength: 2,
384 reg: regInfo{
385 inputs: []regMask{buildReg("R20")},
386 clobbers: buildReg("R20 R1"),
387 },
388 typ: "Mem",
389 faultOnNilArg0: true,
390 },
391
392
393
394
395
396
397
398 {
399 name: "DUFFCOPY",
400 aux: "Int64",
401 argLength: 3,
402 reg: regInfo{
403 inputs: []regMask{buildReg("R21"), buildReg("R20")},
404 clobbers: buildReg("R20 R21 R1"),
405 },
406 typ: "Mem",
407 faultOnNilArg0: true,
408 faultOnNilArg1: true,
409 },
410
411
412
413
414
415
416
417
418
419
420 {
421 name: "LoweredZero",
422 aux: "Int64",
423 argLength: 3,
424 reg: regInfo{
425 inputs: []regMask{buildReg("R20"), gp},
426 clobbers: buildReg("R20"),
427 },
428 typ: "Mem",
429 faultOnNilArg0: true,
430 },
431
432
433
434
435
436
437
438
439
440
441
442
443
444 {
445 name: "LoweredMove",
446 aux: "Int64",
447 argLength: 4,
448 reg: regInfo{
449 inputs: []regMask{buildReg("R21"), buildReg("R20"), gp},
450 clobbers: buildReg("R20 R21"),
451 },
452 typ: "Mem",
453 faultOnNilArg0: true,
454 faultOnNilArg1: true,
455 },
456
457
458
459
460 {name: "LoweredAtomicLoad8", argLength: 2, reg: gpload, faultOnNilArg0: true},
461 {name: "LoweredAtomicLoad32", argLength: 2, reg: gpload, faultOnNilArg0: true},
462 {name: "LoweredAtomicLoad64", argLength: 2, reg: gpload, faultOnNilArg0: true},
463
464
465
466 {name: "LoweredAtomicStore8", argLength: 3, reg: gpstore, faultOnNilArg0: true, hasSideEffects: true},
467 {name: "LoweredAtomicStore32", argLength: 3, reg: gpstore, faultOnNilArg0: true, hasSideEffects: true},
468 {name: "LoweredAtomicStore64", argLength: 3, reg: gpstore, faultOnNilArg0: true, hasSideEffects: true},
469 {name: "LoweredAtomicStore8Variant", argLength: 3, reg: gpstore, faultOnNilArg0: true, hasSideEffects: true},
470 {name: "LoweredAtomicStore32Variant", argLength: 3, reg: gpstore, faultOnNilArg0: true, hasSideEffects: true},
471 {name: "LoweredAtomicStore64Variant", argLength: 3, reg: gpstore, faultOnNilArg0: true, hasSideEffects: true},
472
473
474
475 {name: "LoweredAtomicExchange32", argLength: 3, reg: gpxchg, resultNotInArgs: true, faultOnNilArg0: true, hasSideEffects: true},
476 {name: "LoweredAtomicExchange64", argLength: 3, reg: gpxchg, resultNotInArgs: true, faultOnNilArg0: true, hasSideEffects: true},
477
478
479
480
481 {name: "LoweredAtomicExchange8Variant", argLength: 3, reg: gpxchg, resultNotInArgs: true, faultOnNilArg0: true, hasSideEffects: true},
482
483
484
485 {name: "LoweredAtomicAdd32", argLength: 3, reg: gpxchg, resultNotInArgs: true, faultOnNilArg0: true, hasSideEffects: true},
486 {name: "LoweredAtomicAdd64", argLength: 3, reg: gpxchg, resultNotInArgs: true, faultOnNilArg0: true, hasSideEffects: true},
487
488
489
490
491
492
493
494
495
496
497
498
499
500
501
502
503
504 {name: "LoweredAtomicCas32", argLength: 4, reg: gpcas, resultNotInArgs: true, faultOnNilArg0: true, hasSideEffects: true, unsafePoint: true},
505 {name: "LoweredAtomicCas64", argLength: 4, reg: gpcas, resultNotInArgs: true, faultOnNilArg0: true, hasSideEffects: true, unsafePoint: true},
506
507
508
509
510
511
512
513
514
515
516
517
518
519
520
521 {name: "LoweredAtomicCas64Variant", argLength: 4, reg: gpcas, resultNotInArgs: true, faultOnNilArg0: true, hasSideEffects: true, unsafePoint: true},
522 {name: "LoweredAtomicCas32Variant", argLength: 4, reg: gpcas, resultNotInArgs: true, faultOnNilArg0: true, hasSideEffects: true, unsafePoint: true},
523
524
525
526 {name: "LoweredAtomicAnd32", argLength: 3, reg: gpxchg, asm: "AMANDDBW", resultNotInArgs: true, faultOnNilArg0: true, hasSideEffects: true},
527 {name: "LoweredAtomicOr32", argLength: 3, reg: gpxchg, asm: "AMORDBW", resultNotInArgs: true, faultOnNilArg0: true, hasSideEffects: true},
528
529
530
531 {name: "LoweredAtomicAnd32value", argLength: 3, reg: gpxchg, asm: "AMANDDBW", resultNotInArgs: true, faultOnNilArg0: true, hasSideEffects: true},
532 {name: "LoweredAtomicAnd64value", argLength: 3, reg: gpxchg, asm: "AMANDDBV", resultNotInArgs: true, faultOnNilArg0: true, hasSideEffects: true},
533 {name: "LoweredAtomicOr32value", argLength: 3, reg: gpxchg, asm: "AMORDBW", resultNotInArgs: true, faultOnNilArg0: true, hasSideEffects: true},
534 {name: "LoweredAtomicOr64value", argLength: 3, reg: gpxchg, asm: "AMORDBV", resultNotInArgs: true, faultOnNilArg0: true, hasSideEffects: true},
535
536
537 {name: "LoweredNilCheck", argLength: 2, reg: regInfo{inputs: []regMask{gpg}}, nilCheck: true, faultOnNilArg0: true},
538
539 {name: "FPFlagTrue", argLength: 1, reg: readflags},
540 {name: "FPFlagFalse", argLength: 1, reg: readflags},
541
542
543
544
545 {name: "LoweredGetClosurePtr", reg: regInfo{outputs: []regMask{buildReg("R29")}}, zeroWidth: true},
546
547
548 {name: "LoweredGetCallerSP", argLength: 1, reg: gp01, rematerializeable: true},
549
550
551
552
553
554 {name: "LoweredGetCallerPC", reg: gp01, rematerializeable: true},
555
556
557
558
559
560
561 {name: "LoweredWB", argLength: 1, reg: regInfo{clobbers: (callerSave &^ gpg) | buildReg("R1"), outputs: []regMask{buildReg("R29")}}, clobberFlags: true, aux: "Int64"},
562
563
564 {name: "LoweredPubBarrier", argLength: 1, asm: "DBAR", hasSideEffects: true},
565
566
567
568
569 {name: "LoweredPanicBoundsA", argLength: 3, aux: "Int64", reg: regInfo{inputs: []regMask{r3, r4}}, typ: "Mem", call: true},
570 {name: "LoweredPanicBoundsB", argLength: 3, aux: "Int64", reg: regInfo{inputs: []regMask{r2, r3}}, typ: "Mem", call: true},
571 {name: "LoweredPanicBoundsC", argLength: 3, aux: "Int64", reg: regInfo{inputs: []regMask{r1, r2}}, typ: "Mem", call: true},
572
573
574
575
576
577
578 {name: "PRELD", argLength: 2, aux: "Int64", reg: preldreg, asm: "PRELD", hasSideEffects: true},
579 {name: "PRELDX", argLength: 2, aux: "Int64", reg: preldreg, asm: "PRELDX", hasSideEffects: true},
580 }
581
582 blocks := []blockData{
583 {name: "EQ", controls: 1},
584 {name: "NE", controls: 1},
585 {name: "LTZ", controls: 1},
586 {name: "LEZ", controls: 1},
587 {name: "GTZ", controls: 1},
588 {name: "GEZ", controls: 1},
589 {name: "FPT", controls: 1},
590 {name: "FPF", controls: 1},
591 {name: "BEQ", controls: 2},
592 {name: "BNE", controls: 2},
593 {name: "BGE", controls: 2},
594 {name: "BLT", controls: 2},
595 {name: "BGEU", controls: 2},
596 {name: "BLTU", controls: 2},
597 }
598
599 archs = append(archs, arch{
600 name: "LOONG64",
601 pkg: "cmd/internal/obj/loong64",
602 genfile: "../../loong64/ssa.go",
603 ops: ops,
604 blocks: blocks,
605 regnames: regNamesLOONG64,
606
607 ParamIntRegNames: "R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19",
608 ParamFloatRegNames: "F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15",
609 gpregmask: gp,
610 fpregmask: fp,
611 framepointerreg: -1,
612 linkreg: int8(num["R1"]),
613 })
614 }
615
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